Inventor

LI YANRU

US52 patents

⚠️ This page may combine multiple inventors who share the name “LI YANRU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI YANRU

QUALCOMM INC

Systems and methods to refresh DRAM based on temperature and based on calibration data

Kernel masking of DRAM defects

Non-volatile random access memory with gated security access

Partial refresh technique to save memory refresh power

Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array

Systems and methods for recovering from uncorrected DRAM bit errors

System and method for memory channel interleaving with selective power or performance optimization

Protected data streaming between memories

Partial refresh technique to save memory refresh power

Partial refresh technique to save memory refresh power

Memory access management for low-power use cases of a system on chip via secure non-volatile random access memory

Systems and methods for improved error correction in a refreshable memory

Method and apparatus for virtualized control of a shared system cache

Systems and methods for optimizing memory power consumption in a heterogeneous system memory

Systems and methods for implementing error correcting code regions in a memory

Systems, methods, and computer programs for resolving dram defects

Power-reducing memory subsystem having a system cache and local resource management

Method and apparatus for in-system management and repair of semi-conductor memory failure

Dual host embedded shared device controller

Using USB signaling to trigger a device to enter a mode of operation

Method and apparatus for a shared cache with dynamic partitioning

Systems and methods for reducing volatile memory standby power in a portable computing device

Partial refresh technique to save memory refresh power

Coincident memory bank access via cross connected shared bank resources

Dynamic mapping of applications on NVRAM/DRAM hybrid memory

Boot time determination of calibration parameters for a component coupled to a system-on-chip

Boot time determination of calibration parameters for a component coupled to a system-on-chip

Selectable boot CPU

Methods and apparatus for in-memory device access control

Adaptive power management of dynamic random access memory

Systems and methods for reducing memory power consumption via pre-filled DRAM values

Power-reducing memory subsystem having a system cache and local resource management

System and method for flash read cache with adaptive pre-fetch

Systems and methods for reducing memory failures

Using USB signaling to trigger a device to enter a mode of operation

Systems and methods for providing power-efficient file system operation to a non-volatile block memory

Write access control for double data rate write-x/datacopy0 commands

Selective volatile memory refresh via memory-side data valid indication

Preemptive decompression scheduling for a NAND storage device

System and method for booting within a heterogeneous memory environment

CONTEMPORARY AMPEREX TECHNOLOGY CO LTD

Battery heating system and control method thereof

Battery heating system and control method thereof

Thermal management method for battery pack

Thermal management system for battery pack and thermal management system for electric vehicle

Battery heating system

INTEL CORP

Dynamic prioritization of system-on-chip interconnect traffic using information from an operating system and hardware

Bypassing cache memory in a write transaction in a system with multi-level memory

Read-with-invalidate modified data in a cache line in a cache memory

GOOGLE LLC

Using memory protection data

INST OF MICROELECTRONICS CAS

Multi-state memory and method for manufacturing the same