Inventor

SUH JUNGWON

US92 patents

⚠️ This page may combine multiple inventors who share the name “SUH JUNGWON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUH JUNGWON

QUALCOMM INC

Kernel masking of DRAM defects

System and memory with configurable metadata portion

Partial refresh technique to save memory refresh power

Link error correction in memory system

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

Low-power clocking for a high-speed memory interface

Method and apparatus for refreshing a memory cell

Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array

Mixed memory type hybrid cache

System-in-package with interposer pitch adapter

DRAM sub-array level refresh

Separate link and array error correction in a memory system

DRAM sub-array level autonomic refresh memory controller optimization

Non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

Low power memory system using dual input-output voltage supplies

Partial refresh technique to save memory refresh power

Power saving techniques for memory systems by consolidating data in data lanes of a memory bus

Partial refresh technique to save memory refresh power

Unified memory controller for heterogeneous memory on a multi-chip package

Method and apparatus for in-system repair of memory in burst refresh

Split write operation for resistive memory cache

Vertically stackable dies having chip identifier structures

Split write operation for resistive memory cache

System and method to dynamically determine a timing parameter of a memory device

Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems

Enhanced data clock operations in memory

Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns

Protecting an ECC location when transmitting correction data across a memory link

Method and apparatus for in-system management and repair of semi-conductor memory failure

Dynamic control of signaling power based on an error rate

Methods and apparatuses for in-system field repair and recovery from memory failures

Reducing latency in pseudo channel based memory systems

INFINEON TECHNOLOGIES AG

Memory with auto refresh to designated banks

Sensing current recycling method during self-refresh

Twin-cell bit line sensing configuration

Clock stop detector

Voltage down converter for low voltage operation

Circuit including a deskew circuit for asymmetrically delaying rising and falling edges

Memory data bus structure and method of transferring information with plural memory banks

Voltage trimming circuit

Memory device and method of reading data from a memory cell

SUH JUNGWON

Vertically stackable dies having chip identifier structures

Vertically stackable dies having chip identifier structures

Embedded DRAM having low power self-correction capability

HAO WUYANG

Method and apparatus to provide a clock signal to a charge pump

Resistance based memory having two-diode access device

SAMSUNG ELECTRONICS CO LTD

Method for performing function using sensor data and electronic device for providing same

Electronic device including a plurality of touch displays and method for changing status thereof

RAO HARI M

Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction

CHUN DEXTER T

SerDes power throttling as a function of detected error rate