Inventor

LI KUN-MU

TW70 patents

⚠️ This page may combine multiple inventors who share the name “LI KUN-MU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LI KUN-MU

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor structure with blocking layer and method for forming the same

Semiconductor device, static random access memory cell and manufacturing method of semiconductor device

MOS devices having epitaxy regions with reduced facets

Method of forming epitaxial fin structures of finFET

Integrated circuit and manufacturing method thereof

Method of fabricating a semiconductor device structure

Semiconductor device and manufacturing method thereof

Semiconductor structure and fabricating method thereof

Germanium profile for channel strain

MOS devices with non-uniform P-type impurity profile

Source and drain stressors with recessed top surfaces

Transistor strain-inducing scheme

Method of forming a contact structure for a FinFET semiconductor device

Semiconductor device having epitaxy source/drain regions

Epitaxial fin structures of finFET having an epitaxial buffer region and an epitaxial capping region

Semiconductor device and manufacturing method thereof

Epitaxial fin structures having an epitaxial buffer region and an epitaxial capping region

FinFET device and method

Epitaxial source/drain structure and method of forming same

Profile design for improved device performance

Semiconductor device and manufacturing method thereof

Source and drain stressors with recessed top surfaces

Source and drain stressors with recessed top surfaces

MOS devices having epitaxy regions with reduced facets

Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof

Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration

Semiconductor structure and fabricating method thereof

MOS devices having epitaxy regions with reduced facets

Contact structure for FinFET semiconductor device

Epitaxial fin structures of FINFET having an epitaxial buffer region and an epitaxial capping region

Semiconductor device having epitaxy source/drain regions

Semiconductor device

Epitaxial source/drain structure and method of forming same

Semiconductor device and manufacturing method thereof

Doping profile for strained source/drain region

Epitaxial source/drain structure and method of forming same

Semiconductor device and manufacturing method thereof

Source and drain stressors with recessed top surfaces

MOS devices having epitaxy regions with reduced facets

Static random access memory cell and manufacturing method thereof

Manufacturing method of integrated circuit

MOS devices having epitaxy regions with reduced facets

Semiconductor device and manufacturing method thereof

Source/drain regions of FinFET devices and methods of forming same

TAIWAN SEMICONDUCTOR MFG

Structure and method for semiconductor device

MOS device having source and drain regions with embedded germanium-containing diffusion barrier

MOS devices having epitaxy regions with reduced facets

Reducing pattern loading effect in epitaxy

Source/drain structures and methods of forming same

Modulating germanium percentage in MOS devices