Inventor

BATUDE PERRINE

FR24 patents

⚠️ This page may combine multiple inventors who share the name “BATUDE PERRINE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BATUDE PERRINE

COMMISSARIAT ENERGIE ATOMIQUE

SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable

Method of manufacturing an optoelectronic device comprising a plurality of diodes

Method for doping source and drain regions of a transistor by means of selective amorphisation

Method for forming doped areas under transistor spacers

Method for manufacturing a transistor in which the strain applied to the channel is increased

Recrystallization of source and drain blocks from above

Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor

Method for manufacturing pairs of CMOS transistors of the “fin-FET” type at low temperatures

Method of manufacturing an optoelectronic device comprising a plurality of diodes and an electronic circuit for controlling these diodes

3D circuit provided with mesa isolation for the ground plane zone

Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer

Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions

Image sensor formed in sequential 3D technology

3D circuit transistors with flipped gate

Transistor with controlled overlap of access regions

Method of manufacturing a dopant transistor located vertically on the gate

Integrated circuit having a plurality of active layers and method of fabricating the same

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Method for producing a field effect transistor including forming a gate after forming the source and drain

Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate

ST MICROELECTRONICS SA

Method of making a 3D integrated circuit

Method for forming a via contacting several levels of semiconductor layers

AUGENDRE EMMANUEL

Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit

BATUDE PERRINE

Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT

Commissariat à l'Energie Atomique et aux Energies Alternatives

Fabrication method of a stack of electronic devices