Inventor

VINET MAUD

FR92 patents

⚠️ This page may combine multiple inventors who share the name “VINET MAUD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VINET MAUD

COMMISSARIAT ENERGIE ATOMIQUE

SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable

Method for producing a transistor structure with superimposed nanowires and with a surrounding gate

Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor

Strained-channel transistor device

Quantum device with spin qubits

Microelectronic device provided with transistors coated with a piezoelectric layer

Process for producing FET transistors

Method of manufacturing a LED matrix display device

Method for making a transistor in a stack of superimposed semiconductor layers

CMOS in situ doped flow with independently tunable spacer thickness

Low leakage dual STI integrated circuit including FDSOI transistors

Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same

Method for producing a silicon-germanium film with variable germanium content

Method of making a semiconductor layer having at least two different thicknesses

Electronic component with multiple quantum islands

Method for forming doped areas under transistor spacers

UTBB CMOS imager having a diode junction in a photosensitive area thereof

Method for producing a component comprising at least one germanium-based element and component obtained by such a method

Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same

Transistor with coupled gate and ground plane

Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layer

Method for producing a transistor with metallic source and drain

Method of producing a transistor

Method of making a quantum device

Chip with bifunctional routing and associated method of manufacturing

Method of manufacturing an electronic component including multiple quantum dots

Suspended-gate MOS transistor with non-volatile operation

Non-volatile SRAM memory cell equipped with mobile gate transistors and piezoelectric operation

Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals localised with precision

Quantum device comprising FET transistors and qubits co-integrated on the same substrate

Manufacturing process for a transistor made of thin layers

Internal via with improved contact for upper semi-conductor layer of a 3D circuit

Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location

IBM

Dual shallow trench isolation liner for preventing electrical shorts

Contact isolation scheme for thin buried oxide substrate devices

Dual shallow trench isolation liner for preventing electrical shorts

Dual shallow trench isolation liner for preventing electrical shorts

VINET MAUD

Method for making asymmetric double-gate transistors

Transistor with counter-electrode connection amalgamated with the source/drain contact

Device for measuring metal/semiconductor contact resistivity

Method for fabricating asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate

ST MICROELECTRONICS SA

Method for manufacturing a fin MOS transistor

Method for manufacturing a fin MOS transistor

AUGENDRE EMMANUEL

Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit

BATUDE PERRINE

Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT

ST MICROELECTRONICS INC

Uniaxially-strained FD-SOI finFET

DORIS BRUCE B

Dual shallow trench isolation liner for preventing electrical shorts

THOMAS OLIVIER

Memory cell provided with dual-gate transistors, with independent asymmetric gates

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT

Method of etching a crystalline semiconductor material by ion implantation and then chemical etching based on hydrogen chloride

COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERG

Method for producing an electronic component with double quantum dots