Inventor

COHEN EARL T

US149 patents

⚠️ This page may combine multiple inventors who share the name “COHEN EARL T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COHEN EARL T

EXPONENTIAL TECHN INC

Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU

Master-slave cache system with de-coupled data and tag pipelines and loop-back

Block-based branch prediction using a target finder array storing target sub-addresses

Program watchpoint checking using paging with sub-page validity

Master-slave cache system for instruction and data cache memories

Address tracking and branch resolution in a processor with multiple execution pipelines and instruction stream discontinuities

Sign-extension of immediate constants in an alu

Emulation of segment bounds checking using paging with sub-page validity

Slave cache having sub-line valid bits updated by a master cache

Combined store queue for a master-slave cache system

Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU

Reduced-modulus address generation using sign-extension and correction

Inexact leading-one/leading-zero prediction integrated with a floating-point adder

CISCO TECH INC

Thread interleaving in a multithreaded embedded processor

Thread-aware instruction fetching in a multithreaded embedded processor

Methods and apparatus for maintaining statistic counters and updating a secondary counter storage via a queue for reducing or eliminating overflow of the counters

Error protection for lookup operations performed on ternary content-addressable memory entries

Distributing packets and packets fragments possibly received out of sequence into an expandable set of queues of particular use in packet resequencing and reassembly

Methods and apparatus for simultaneously scheduling multiple priorities of packets

Tokens in token buckets maintained among primary and secondary storages

Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor

SEAGATE TECHNOLOGY LLC

Retention-drift-history-based non-volatile memory read threshold optimization

Optimization of read thresholds for non-volatile memory

Nonvolatile memory data recovery after power failure

Translation layer partitioned between host and controller

Storage address space to NVM address, span, and length mapping/converting

Non-volatile memory program failure recovery via redundant arrays

Flash translation layer with lower write amplification

Scalable data structures for control and management of non-volatile storage

LSI CORP

Self-journaling and hierarchical consistency for non-volatile storage

Read disturb effect determination

Low-density parity-check decoder disparity preprocessing

Partial R-block recycling

BIT MICROSYSTEMS INC

Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations

Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers

Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage

CONEXANT SYSTEMS INC

Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system

Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system

SUN MICROSYSTEMS INC

Method and apparatus for simulation system compiler

Method and apparatus for cycle-based computation

COHEN EARL T

I/O device and computing host interoperation

Zero-one balance management in a solid-state disk controller

CYCLOTOMICS INC

Hard-wired serial Galois field decoder

Probabilistic fade forecasting

MCWILLIAMS THOMAS M

System including a fine-grained memory and a less-fine-grained memory

SCHOONER INFORMATION TECHNOLOGY INC

System including a fine-grained memory and a less-fine-grained memory

ZHONG HAO

LDPC erasure decoding for flash memories

WU YUNXIANG

Soft-decision compensation for flash channel variation

S3 INC

RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU