Inventor

GUPTA RAJESH N

IN28 patents

⚠️ This page may combine multiple inventors who share the name “GUPTA RAJESH N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUPTA RAJESH N

MICRON TECHNOLOGY INC

Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Passing access line structure in a memory device

Vertical access device and apparatuses having a body connection line, and related method of operating the same

Thyristors

Passing access line structure in a memory device

Thyristors, methods of programming thyristors, and methods of forming thyristors

Resistance variable element methods and apparatuses

Apparatuses having a vertical memory cell

Systems and methods for generating logical-to-physical tables for wear-leveling

Memory operations with consideration for wear leveling

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

Thyristor memory and methods of operation

Methods and apparatuses for threshold voltage measurement and related semiconductor devices and systems

Resistance variable element methods and apparatuses

Resistance variable element methods and apparatuses

Memory cells having a common gate terminal

GUPTA RAJESH N

Thyristor memory and methods of operation

Reduction of electrostatic coupling for a thyristor-based memory cell

Gated bipolar junction transistors

Memory cells having a common gate terminal

T RAM SEMICONDUCTOR INC

Semiconductor device with leakage implant and method of fabrication

Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region

RENSSELAER POLYTECH INST

Compact low power complement FETs

NEMATI FARID

Thyristors

TARABBIA MARC LAURENT

Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting