Inventor
CHOUKSEY SIDDHARTH
US22 patents
Patents
22 patentsUS11222977B2Jan 11, 2022
Source/drain diffusion barrier for germanium NMOS transistors
INTEL CORP8 citations85
US12272727B2Apr 8, 2025
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP2 citations74
US11990513B2May 21, 2024
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP2 citations72
US11532706B2Dec 20, 2022
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
INTEL CORP3 citations72
US12255234B2Mar 18, 2025
Integrated circuit structures having germanium-based channels
INTEL CORP0 citations62
US12199142B2Jan 14, 2025
Neighboring gate-all-around integrated circuit structures having conductive contact stressor between epitaxial source or drain regions
INTEL CORP0 citations62
US11923421B2Mar 5, 2024
Integrated circuit structures having germanium-based channels
INTEL CORP0 citations62
US11735670B2Aug 22, 2023
Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors
INTEL CORP0 citations62
US11699756B2Jul 11, 2023
Source/drain diffusion barrier for germanium nMOS transistors
INTEL CORP0 citations62
US11450739B2Sep 20, 2022
Germanium-rich nanowire transistor with relaxed buffer layer
INTEL CORP0 citations62
US11437472B2Sep 6, 2022
Integrated circuit structures having germanium-based channels
INTEL CORP0 citations62
US11189730B2Nov 30, 2021
Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors
INTEL CORP0 citations62
US11101356B2Aug 24, 2021
Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors
INTEL CORP0 citations62
US12119387B2Oct 15, 2024
Low resistance approaches for fabricating contacts and the resulting structures
INTEL CORP1 citations61
US11923290B2Mar 5, 2024
Halogen treatment for NMOS contact resistance improvement
INTEL CORP0 citations59
US12550401B2Feb 10, 2026
Doped STI to reduce source/drain diffusion for germanium NMOS transistors
INTEL CORP0 citations52
US12414339B2Sep 9, 2025
Formation of gate spacers for strained PMOS gate-all-around transistor structures
INTEL CORP0 citations52
US11233148B2Jan 25, 2022
Reducing band-to-band tunneling in semiconductor devices
INTEL CORP0 citations52
US10644112B2May 5, 2020
Systems, methods and devices for isolation for subfin leakage
INTEL CORP0 citations52
US12328927B2Jun 10, 2025
Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures
INTEL CORP0 citations51
US12266570B2Apr 1, 2025
Self-aligned interconnect structures and methods of fabrication
INTEL CORP0 citations51
US11575005B2Feb 7, 2023
Asymmetrical semiconductor nanowire field-effect transistor
INTEL CORP0 citations51