Inventor

PARK HYUN-MOG

KR41 patents

⚠️ This page may combine multiple inventors who share the name “PARK HYUN-MOG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK HYUN-MOG

SAMSUNG ELECTRONICS CO LTD

Semiconductor device

Semiconductor device

Semiconductor device

Three-dimensional semiconductor device having contact plugs penetrating upper adjacent electrodes

NAND-type nonvolatile memory device and related method of manufacture

Semiconductor devices

Semiconductor devices

Semiconductor devices and manufacturing methods of the same

Semiconductor device

Semiconductor devices and manufacturing methods of the same

Semiconductor device

Three-dimensional semiconductor device including a cell array region and a contact region

Semiconductor devices

Vertical memory devices and methods of manufacturing the same

Semiconductor device including gates

Semiconductor device including gates

Semiconductor device

Semiconductor devices

Semiconductor device

Semiconductor device

Method of aligning wafers, method of bonding wafers using the same, and apparatus for performing the same

Vertical memory device

INTEL CORP

Air gap interconnect method

Creating air gap in multi-level metal interconnects using electron beam to remove sacrificial material

Forming thin hard mask over air gap or porous dielectric

Interconnect structure for an integrated circuit and method of fabrication

Semiconductor device having a region of a material which is vaporized upon exposing to ultraviolet radiation

Method of making a semiconductor device by forming a masking layer with a tapered etch profile

Method of forming an air gap within a structure by exposing an ultraviolet sensitive material to ultraviolet radiation

Sealing porous dielectric material using plasma-induced surface polymerization

Air gap interconnect structure and method

Method of patterning a porous dielectric material

Method of making a semiconductor device by forming a masking layer with a tapered etch profile

Method for controlling etch bias of carbon doped oxide films

Interconnect structure for an integrated circuit and method of fabrication

Forming a porous dielectric layer and structures formed thereby

Via etch process

Dielectric with sidewall passivating layer

Supercritical carbon dioxide to reduce line edge roughness

Forming a porous dielectric layer and structures formed thereby

YOON YOUNG-BAE

Vertical memory devices and methods of manufacturing the same