Inventor

TAI YING YU

US92 patents

⚠️ This page may combine multiple inventors who share the name “TAI YING YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAI YING YU

MICRON TECHNOLOGY INC

Transferring data between clock domains using pulses across a queue

Write buffer management

Refreshing data stored at a memory component based on a memory component characteristic component

Temperature-based media management for memory components

Internal management traffic regulation for memory sub-systems

Performing hybrid wear leveling operations based on a sub-total write counter

Scanning techniques for a media-management operation of a memory sub-system

Hardware based status collector acceleration engine for memory sub-system operations

Unmap data pattern for coarse mapping memory sub-system

Memory sub-system including an in package sequencer separate from a controller

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

Performing hybrid wear leveling operations based on a sub-total write counter

Cross point array memory in a non-volatile dual in-line memory module

Corrective read with parallel auto-read calibration in a memory sub-system

Hybrid wear leveling for in-place data replacement media

Scheduling of read operations and write operations based on a data bus mode

Adaptive media management for memory systems

Temperature-based media management for memory components

Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations

Scheduling of read operations and write operations based on a data bus mode

Scanning techniques for a media-management operation of a memory sub-system

Reset and replay of memory sub-system controller in a memory sub-system

Metadata-assisted encoding and decoding for a memory sub-system

Multi-level wear leveling for non-volatile memory

Performing hybrid wear leveling operations based on a sub-total write counter

Early decoding termination for a memory sub-system

Management of write operations in a non-volatile memory device using a variable pre-read voltage level

Refreshing data stored at a memory component based on a memory component characteristic component

Changing of error correction codes based on the wear of a memory sub-system

Hybrid wear leveling for in-place data replacement media

Biased sampling methodology for wear leveling

Maintaining data consistency in a memory subsystem that uses hybrid wear leveling operations

Hybrid iterative error correcting and redundancy decoding operations for memory sub-systems

Reset and replay of memory sub-system controller in a memory sub-system

Management of write operations in a non-volatile memory device using a variable pre-read voltage level

Refreshing data stored at a memory component based on a memory component characteristic component

SANDISK ENTPR IP LLC

Method and system of reading threshold voltage equalization

Universal and reconfigurable QC-LDPC encoder

Syndrome layered decoding for LDPC codes

High-speed multi-block-row layered decoder for low density parity check (LDPC) codes

Encoder with transform architecture for LDPC codes over subfields using message mapping

Encoder for quasi-cyclic low-density parity-check codes over subfields using fourier transform

VIA TECH INC

Non-volatile memory apparatus and address classification method thereof

Non-volatile memory device and control method thereof

Low-density parity-check apparatus and matrix trapping set breaking method

Non-volatile memory apparatus and on-the-fly self-adaptive read voltage adjustment method thereof

TAI YING YU

Soft information generation for memory systems

Adaptive read comparison signal generation for memory systems

Statistical read comparison signal generation for memory systems

CHEN XIAOHENG

Compressing data from multiple reads for error control management in memory systems