Inventor

CHOI YOUN SUNG

US24 patents

⚠️ This page may combine multiple inventors who share the name “CHOI YOUN SUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOI YOUN SUNG

TEXAS INSTRUMENTS INC

Silicide formation due to improved SiGe faceting

Method of printing multiple structure widths using spacer double patterning

Integration of finFET device

Integrated circuit with dual stress liner boundary

Drain induced barrier lowering with anti-punch-through implant

Silicide formation due to improved SiGe faceting

Integration of analog transistor

Integration of analog transistor

Method for improving device performance using dual stress liner boundary

Integrated circuit with dual stress liner boundary

Silicide formation due to improved SiGe faceting

Integration of analog transistor

QUALCOMM INC

Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells

Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout

Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions

Leakage current reduction in polysilicon-on-active-edge structures

Sensor for gate leakage detection

SRAM source-drain structure

Systems and methods for fabrication of gated diodes with selective epitaxial growth

CHOI YOUN SUNG

Method for improving device performance using dual stress liner boundary

Scribe line test modules for in-line monitoring of context dependent effects for ICs including MOS devices

ZHAO SONG

Integrated circuit having silicide block resistor

BALDWIN GREGORY CHARLES

On-die parametric test modules for in-line monitoring of context dependent effects