Inventor
AGGARWAL ANIL
US33 patents
⚠️ This page may combine multiple inventors who share the name “AGGARWAL ANIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS7328293B2Feb 5, 2008
Queued locks using monitor-memory wait
INTEL CORP47 citations96
US7818596B2Oct 19, 2010
Method and apparatus of power management of processor
INTEL CORP53 citations94
US7213093B2May 1, 2007
Queued locks using monitor-memory wait
INTEL CORP22 citations93
US7962771B2Jun 14, 2011
Method, system, and apparatus for rerouting interrupts in a multi-core processor
INTEL CORP28 citations92
US7810083B2Oct 5, 2010
Mechanism to emulate user-level multithreading on an OS-sequestered sequencer
INTEL CORP25 citations92
US7194540B2Mar 20, 2007
Mechanism for allowing multiple entities on the same host to handle messages of same service class in a cluster
INTEL CORP21 citations90
US7640384B2Dec 29, 2009
Queued locks using monitor-memory wait
INTEL CORP10 citations84
US7917789B2Mar 29, 2011
System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms
INTEL CORP15 citations83
US7849465B2Dec 7, 2010
Programmable event driven yield mechanism which may activate service threads
INTEL CORP18 citations83
US8028295B2Sep 27, 2011
Apparatus, system, and method for persistent user-level thread
INTEL CORP4 citations74
US11221857B2Jan 11, 2022
Collaborative processor and system performance and power management
INTEL CORP0 citations73
US10372197B2Aug 6, 2019
User level control of power management policies
INTEL CORP3 citations73
US10275260B2Apr 30, 2019
Collaborative processor and system performance and power management
INTEL CORP1 citations73
US8874947B2Oct 28, 2014
Method and apparatus of power management of processor
INTEL CORP4 citations73
US10007528B2Jun 26, 2018
Computing platform interface with memory management
INTEL CORP1 citations62
US9535487B2Jan 3, 2017
User level control of power management policies
INTEL CORP1 citations62
US9170624B2Oct 27, 2015
User level control of power management policies
INTEL CORP3 citations62
US9875102B2Jan 23, 2018
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9766891B2Sep 19, 2017
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9383997B2Jul 5, 2016
Apparatus, system, and method for persistent user-level thread
INTEL CORP0 citations52
US9459683B2Oct 4, 2016
Techniques for entering a low power state
INTEL CORP0 citations48
THERIEN GUY M
3 patentsUS9454379B2Sep 27, 2016
Collaborative processor and system performance and power management
THERIEN GUY M3 citations83
US9442739B2Sep 13, 2016
Collaborative processor and system performance and power management
THERIEN GUY M4 citations83
US10108433B2Oct 23, 2018
Collaborative processor and system performance and power management
THERIEN GUY M0 citations62