Inventor

DAS SHARMA DEBENDRA

US170 patents

⚠️ This page may combine multiple inventors who share the name “DAS SHARMA DEBENDRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DAS SHARMA DEBENDRA

INTEL CORP

PCI express enhancements and extensions

Multi-protocol support on common physical layer

Forward error correction mechanism for data transmission across multi-lane links

Multichip package link

Pooled memory address translation

Using asymmetric lanes dynamically in a multi-lane serial link

Providing high availability in a PCI-Express™ link in the presence of lane faults

High performance interconnect

PCI express enhancements and extensions

PCI express enhancements and extensions

Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect

Flit-based packetization

Bypassing equalization at lower data rates

Forward error correction mechanism for peripheral component interconnect-express (PCI-e)

High performance interconnect

Multiple transaction data flow control unit for high-speed interconnect

Bypassing equalization at lower data rates

Controlling partial link width states for multilane links

Low latency multi-protocol retimers

Width and frequency conversion with PHY layer devices in PCI-express

Interconnect retimer enhancements

Applying framing rules for a high speed data link

Low latency multi-protocol retimers

Method and apparatus for dynamically allocating storage resources to compute nodes

Shared buffered memory routing

Redriver link testing

Atomic operations in PCI express

Assisted coherent shared memory

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Transaction layer packet compression

High performance interconnect

Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect

Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface

Flex bus protocol negotiation and enabling sequence

Architecture for software defined interconnect switch

Multichip package link

Live error recovery

AJANOVIC JASMIN

PCI express enhancements and extensions

PCI express enhancements and extensions

PCI express enhancements and extensions including device window caching

PCI express enhancements and extensions

PCI express enhancements and extensions including transactions having prefetch parameters

PCI express enhancements and extensions

HEWLETT PACKARD DEVELOPMENT CO

Static end to end retransmit apparatus and method

Virtualization of computer system interconnects

SAFRANEK ROBERT J

Multiple transaction data flow control unit for high-speed interconnect

Implementing quickpath interconnect protocol over a PCIe interface

PARDO ILAN

Compression format for high bandwidth dictionary compression