Inventor

ABOU-KHALIL MICHEL J

US52 patents

⚠️ This page may combine multiple inventors who share the name “ABOU-KHALIL MICHEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABOU-KHALIL MICHEL J

IBM

Design structures for high-voltage integrated circuits

Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures

Low leakage electrostatic discharge protection circuit

Structure and circuit technique for uniform triggering of multifinger semiconductor devices with tunable trigger voltage

Design structure for uniform triggering of multifinger semiconductor devices with tunable trigger voltage

Thin body switch transistor

Through silicon via repair

E-fuse used to disable a triggering network

Bidirectional electrostatic discharge protection structure for high voltage applications

Structures, methods and applications for electrical pulse anneal processes

Structures, methods and applications for electrical pulse anneal processes

Silicon controlled rectifiers (SCR), methods of manufacture and design structures

Structures, methods and applications for electrical pulse anneal processes

Structures, methods and applications for electrical pulse anneal processes

Semiconductor-on-insulator device with asymmetric structure

Metal-insulator-metal capacitors with high capacitance density

Semiconductor structures with thinned junctions and methods of manufacture

Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates

Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse)

ABOU-KHALIL MICHEL J

Metal-insulator-metal capacitors with high capacitance density

RC-triggered semiconductor controlled rectifier for ESD protection of signal pads

Structures, methods and applications for electrical pulse anneal processes

Semiconductor structures with thinned junctions and methods of manufacture

Field effect transistor having ohmic body contact(s), an integrated circuit structure incorporating stacked field effect transistors with such ohmic body contacts and associated methods

Programmable electrical fuse

Low leakage, low capacitance electrostatic discharge (ESD) silicon controlled recitifer (SCR), methods of manufacture and design structure

Gate dielectric breakdown protection during ESD events

Bi-directional back-to-back stacked SCR for high-voltage pin ESD protection, methods of manufacture and design structures

Semiconductor device heat dissipation structure

Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures

Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates

Silicon controlled rectifiers (SCR), methods of manufacture and design structures

Semiconductor-on-insulator device with asymmetric structure

Through silicon via repair

Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor

Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs

GLOBALFOUNDRIES US INC

Field-effect transistors with a polycrystalline body in a shallow trench isolation region

Multi-depth regions of high resistivity in a semiconductor substrate

Vertically stacked field effect transistors

Vertically stacked field effect transistors

Efuse inside and gate structure on triple-well region

Field-effect transistors with a body pedestal

High electron mobility transistors

Semiconductor device structures with a substrate biasing scheme

Buried damage layers for electrical isolation

Semiconductor structures including stacked depleted and high resistivity regions

Transistors with sectioned extension regions

Device with dual isolation structure

GLOBALFOUNDRIES INC

Embedded polysilicon resistors with crystallization barriers

Field-effect transistors with laterally-serpentine gates