Inventor

MEIXNER ALBERT

US73 patents

⚠️ This page may combine multiple inventors who share the name “MEIXNER ALBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEIXNER ALBERT

GOOGLE LLC

Statistics operations on two dimensional image processor

Convolutional neural network on programmable two dimensional image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Line buffer unit for image processor

Sheet generator for image processor

Virtual linebuffers for image signal processors

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Two dimensional masked shift instruction

Convolutional neural network on programmable two dimensional image processor

Compiler managed memory for image processor

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Virtual linebuffers for image signal processors

Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform

Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform

Energy efficient processor core architecture for image processor

Compiler managed memory for image processor

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Architecture for high performance, power efficient, programmable image processing

Macro I/O unit for image processor

Macro I/O unit for image processor

Multi-functional execution lane for image processor

Configurable and programmable image processor unit

Two dimensional masked shift instruction

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Configuration of application software on multi-core image processor

Program code transformations to improve image processor runtime efficiency

Image processor complex transfer functions

Image processor complex transfer functions

Convolutional neural network on programmable two dimensional image processor

Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register

Line buffer unit for image processor

Two dimensional shift array for image processor

Sheet generator for image processor

Energy efficient processor core architecture for image processor

Configurable and programmable image processor unit

Way partitioning for a system-level cache

Way partitioning for a system-level cache

GOOGLE INC

Energy efficient processor core architecture for image processor

Two dimensional shift array for image processor

Line buffer unit for image processor

Virtual linebuffers for image signal processors

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Multi-functional execution lane for image processor

NVIDIA CORP

Variable fragment shading with surface recasting

System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same

NURO INC

Methods and apparatus for providing redundant networking capabilities for teleoperations

Image quality enhancement for autonomous vehicle remote operations

NVIDIA

Tile shader for screen space, a method of rendering and a graphics processing unit employing the tile shader