Inventor

RANA VIKAS

IN51 patents

⚠️ This page may combine multiple inventors who share the name “RANA VIKAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANA VIKAS

ST MICROELECTRONICS INT NV

Circuit for level shifting a clock signal using a voltage multiplier

Voltage doubling circuit and charge pump applications for the voltage doubling circuit

Single stage cascoded voltage level shifting circuit

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

CMOS oscillator having stable frequency with process, temperature, and voltage variation

Positive and negative charge pump control

Charge pump circuit configured for positive and negative voltage generation

High range positive voltage level shifter using low voltage devices

Single-stage CMOS-based voltage quadrupler circuit

Circuit for level shifting a clock signal using a voltage multiplier

Non-volatile memory (NVM) with dummy rows supporting memory operations

Body bias multiplexer for stress-free transmission of positive and negative supplies

Non-volatile memory with reduced sub-threshold leakage during program and erase operations

Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

Positive and negative charge pump control

Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof

Positive and negative charge pump control

Low input supply and low output impedance charge pump circuit configured for positive and negative voltage generation

Charge pump circuit configured for positive and negative voltage generation

Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation

Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof

Circuit for generating and trimming phases for memory cell read operations

Circuit and method for on-chip leakage detection and compensation for memories

Memory circuit arrangement for accurate and secure read

Memory circuit arrangement for accurate and secure read

Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory

Multi-stage charge pump circuit operating to simultaneously generate both a positive voltage and a negative voltage

Device and method to generate bias voltages in non-volatile memory

Circuit and method for controlled discharge of a high (positive or negative) voltage charge pump

Circuit and method to detect word-line leakage and process defects in non-volatile memory array

NMOS-based negative charge pump circuit

Word-line driver for memory

Selectively configurable charge pump

Circuit and method for constant slew rate in high voltage charge pumps

ST MICROELECTRONICS SRL

Row decoder for non-volatile memory devices and related methods

Regulator of a sense amplifier

Memory device including decoder for a program pulse and related methods

Circuit for generating and trimming phases for memory cell read operations

Circuit for generating and trimming phases for memory cell read operations

Circuit and method for process and temperature compensated read voltage for non-volatile memory

Memory device including decoder for a program pulse and related methods

Memory device including decoder for a program pulse and related methods

Non-volatile memory device with a program driver circuit including a voltage limiter

Non-volatile memory cell with single poly, floating gate extending over two wells

RANA VIKAS

Negative voltage level shifter circuit

Word line driver for memory

ST MICROELECTRONICS PVT LTD

Multiple output level shifter

High voltage switch with reduced voltage stress at output stage

COUNCIL SCIENT IND RES

Lubricant formulation of carbamoylethyl katira and a process for preparation thereof