Inventor

RAMSBEY MARK

US44 patents

⚠️ This page may combine multiple inventors who share the name “RAMSBEY MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMSBEY MARK

ADVANCED MICRO DEVICES INC

Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory

Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory

Process for fabricating an integrated circuit with a self-aligned contact

Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide

Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device

Process for fabricating high density memory cells using a polysilicon hard mask

Process for fabricating high density memory cells using a metallic hard mask

Method of forming ONO flash memory devices using low energy nitrogen implantation

Integrated method by using high temperature oxide for top oxide and periphery gate oxide

Diode fabrication for ESD/EOS protection

Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor device

PECVD silicon-rich oxide layer for reduced UV charging

Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices

Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

Source bus formation for a flash memory using silicide

Selectively oxidized field oxide region

Nitrogen implant after bit-line formation for ONO flash memory devices

Method of forming ONO flash memory devices using rapid thermal oxidation

Method for removing semiconductor ARC using ARC CMP buffing

Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices

Viable memory cell formed using rapid thermal annealing

Bitline implant utilizing dual poly

Process for fabricating an integrated circuit with a self-aligned contact

Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices

Integration of an ion implant hard mask structure into a process for fabricating high density memory cells

CYPRESS SEMICONDUCTOR CORP

Memory first process flow and device

Memory first process flow and device

Split gate charge trapping memory cells having different select gate and memory gate heights

Memory first process flow and device

Split gate charge trapping memory cells having different select gate and memory gate heights

Memory first process flow and device

Three dimensional capacitor

Use disposable gate cap to form transistors, and split gate charge trapping memory cells

Gate formation memory by planarization

Charge trapping split gate embedded flash memory and associated methods

SPANSION LLC

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

Memory first process flow and device

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

Memory gate landing pad made from dummy features

Method of forming narrowly spaced flash memory contact openings and lithography masks

Process charging protection for split gate charge trapping flash

FASL LLC

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen

NANTERO INC

Resistive change elements using passivating interface gaps and methods for making same