Inventor

PEREGO RICHARD E

US138 patents

⚠️ This page may combine multiple inventors who share the name “PEREGO RICHARD E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEREGO RICHARD E

RAMBUS INC

Method and apparatus for signaling between devices of a memory system

Method and apparatus for signaling between devices of a memory system

Dynamic memory supporting simultaneous refresh and data-access transactions

System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

System featuring memory modules that include an integrated circuit buffer devices

System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices

Memory device supporting a dynamically configurable core organization

Multiple channel modules and bus systems using same

Method and apparatus for coordinating memory operations among diversely-located memory components

Memory system including a point-to-point linked memory subsystem

Timing calibration apparatus and method for a memory device signaling system

Translation lookaside buffer extended to provide physical and main-memory addresses

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Method and apparatus for coordinating memory operations among diversely-located memory components

Memory device with clock multiplier circuit

Method, system and memory controller utilizing adjustable write data delay settings

Method, system and memory controller utilizing adjustable read data delay settings

Memory module

Memory component with terminated and unterminated signaling inputs

Upgradable memory system with reconfigurable interconnect

Dynamic memory supporting simultaneous refresh and data-access transactions

Periodic calibration for communication channels by drift tracking

System having a controller device, a buffer device and a plurality of memory devices

Memory system and device with serialized data transfer

Memory module with termination component

Memory module with termination component

Communication channel calibration for drift conditions

System featuring a master device, a buffer device and a plurality of integrated circuit memory devices

Multiple channel modules and bus systems using same

Coded write masking

Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

Phase adjustment apparatus and method for a memory device signaling system

Memory controller

Memory controller

Memory module

Memory controller that enforces strobe-to-strobe timing offset

Upgradable memory system with reconfigurable interconnect

Communication channel calibration for drift conditions

Periodic calibration for communication channels by drift tracking

Early read after write operation memory device, system and method

Memory module having an integrated circuit buffer device

Integrated circuit buffer device

WARE FREDERICK A

Communication channel calibration for drift conditions

Memory controller with selective data transmission delay

Memory module with termination component

Memory controller device having timing offset capability

Memory controller

Memory module with termination component

PEREGO RICHARD E

Memory controllers, systems, and methods supporting multiple request modes

Memory system with point-to-point request interconnect