Inventor
RENGARAJAN RAJESH
US27 patents
⚠️ This page may combine multiple inventors who share the name “RENGARAJAN RAJESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS6501131B1Dec 31, 2002
Transistors having independently adjustable parameters
IBM95 citations98
US6869866B1Mar 22, 2005
Silicide proximity structures for CMOS device performance improvements
IBM53 citations96
US6740920B2May 25, 2004
Vertical MOSFET with horizontally graded channel doping
IBM27 citations92
US6329704B1Dec 11, 2001
Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
IBM34 citations92
US6127215AOct 3, 2000
Deep pivot mask for enhanced buried-channel PFET performance and reliability
IBM23 citations92
US6521493B1Feb 18, 2003
Semiconductor device with STI sidewall implant
IBM28 citations89
US6426247B1Jul 30, 2002
Low bitline capacitance structure and method of making same
IBM9 citations74
US6387782B2May 14, 2002
Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
IBM6 citations74
US6724053B1Apr 20, 2004
PMOSFET device with localized nitrogen sidewall implantation
IBM12 citations73
US6197632B1Mar 6, 2001
Method for dual sidewall oxidation in high density, high performance DRAMS
IBM14 citations73
US6960523B2Nov 1, 2005
Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device
IBM10 citations71
US7572689B2Aug 11, 2009
Method and structure for reducing induced mechanical stresses
IBM2 citations63
US7314790B2Jan 1, 2008
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
IBM1 citations62
US7161169B2Jan 9, 2007
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
IBM2 citations62
US7883948B2Feb 8, 2011
Method and structure for reducing induced mechanical stresses
IBM0 citations52
US7473607B2Jan 6, 2009
Method of manufacturing a multi-workfunction gates for a CMOS circuit
IBM1 citations52
US7943486B2May 17, 2011
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
IBM0 citations51
US7462525B2Dec 9, 2008
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
IBM0 citations51
SIEMENS AG
4 patentsUS5940717AAug 17, 1999
Recessed shallow trench isolation structure nitride liner and method for making same
SIEMENS AG81 citations96
US6960818B1Nov 1, 2005
Recessed shallow trench isolation structure nitride liner and method for making same
SIEMENS AG24 citations92
US6323103B1Nov 27, 2001
Method for fabricating transistors
SIEMENS AG39 citations92
US6074903AJun 13, 2000
Method for forming electrical isolation for semiconductor devices
SIEMENS AG19 citations84