Inventor
PASDAST GERALD S
US20 patents
Patents
20 patentsUS10552357B2Feb 4, 2020
Multichip package link
INTEL CORP14 citations93
US11581282B2Feb 14, 2023
Serializer-deserializer die for high speed signal interconnect
INTEL CORP10 citations86
US10073808B2Sep 11, 2018
Multichip package link
INTEL CORP11 citations82
US9946676B2Apr 17, 2018
Multichip package link
INTEL CORP8 citations82
US9692402B2Jun 27, 2017
Method, apparatus, system for centering in a high performance interconnect
INTEL CORP10 citations82
US12107060B2Oct 1, 2024
Microelectronic assemblies with inductors in direct bonding regions
INTEL CORP5 citations75
US12062631B2Aug 13, 2024
Microelectronic assemblies with inductors in direct bonding regions
INTEL CORP4 citations74
US12406962B2Sep 2, 2025
Power delivery through capacitor-dies in a multi-layered microelectronic assembly
INTEL CORP2 citations70
US11003610B2May 11, 2021
Multichip package link
INTEL CORP1 citations70
US12519084B2Jan 6, 2026
Forwarded supply voltage for dynamic voltage and frequency scaling with stacked chip packaging architecture
INTEL CORP1 citations63
US12316343B2May 27, 2025
PHY-based retry techniques for die-to-die interfaces
INTEL CORP0 citations62
US11367707B2Jun 21, 2022
Semiconductor package or structure with dual-sided interposers and memory
INTEL CORP1 citations62
US11336559B2May 17, 2022
Fast-lane routing for multi-chip packages
INTEL CORP0 citations62
US12117960B2Oct 15, 2024
Approximate data bus inversion technique for latency sensitive applications
INTEL CORP1 citations61
US12599033B2Apr 7, 2026
Quasi-monolithic integrated packaging architecture with mid-die serializer/deserializer
INTEL CORP0 citations60
US12581968B2Mar 17, 2026
Package architecture of large dies using quasi-monolithic chip layers
INTEL CORP0 citations60
US10461805B2Oct 29, 2019
Valid lane training
INTEL CORP1 citations60
US12266682B2Apr 1, 2025
Capacitors and resistors at direct bonding interfaces in microelectronic assemblies
INTEL CORP0 citations52
US12469820B2Nov 11, 2025
Fine-grained disaggregated server architecture
INTEL CORP0 citations51
US10560081B2Feb 11, 2020
Method, apparatus, system for centering in a high performance interconnect
INTEL CORP0 citations49