Inventor
POWELL GILES V
US13 patents
⚠️ This page may combine multiple inventors who share the name “POWELL GILES V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
7 patentsUS6670825B1Dec 30, 2003
Efficient arrangement of interconnection resources on programmable logic devices
ALTERA CORP39 citations92
US6507216B1Jan 14, 2003
Efficient arrangement of interconnection resources on programmable logic devices
ALTERA CORP22 citations92
US8344496B1Jan 1, 2013
Distributing power with through-silicon-vias
ALTERA CORP13 citations83
US6653862B2Nov 25, 2003
Use of dangling partial lines for interfacing in a PLD
ALTERA CORP11 citations74
US6859065B2Feb 22, 2005
Use of dangling partial lines for interfacing in a PLD
ALTERA CORP4 citations63
US9219483B1Dec 22, 2015
Integrated circuit floorplans
ALTERA CORP0 citations51
US10043716B2Aug 7, 2018
N-well/P-well strap structures
ALTERA CORP0 citations48
CADENCE DESIGN SYSTEMS INC
3 patentsUS9904756B1Feb 27, 2018
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs
CADENCE DESIGN SYSTEMS INC26 citations93
US9652579B1May 16, 2017
Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs
CADENCE DESIGN SYSTEMS INC25 citations93
US9659138B1May 23, 2017
Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques
CADENCE DESIGN SYSTEMS INC18 citations83