Inventor

DIRIL ABDULKADIR UTKU

US41 patents

⚠️ This page may combine multiple inventors who share the name “DIRIL ABDULKADIR UTKU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIRIL ABDULKADIR UTKU

META PLATFORMS INC

Systems and methods for reducing power consumption of convolution operations of artificial neural networks

Systems and methods for quantizing neural networks via periodic regularization functions

Mapping convolution to a matrix processor unit

Mapping convolution to a channel convolution engine

Mapping convolution to a partition channel convolution engine

Static memory allocation in neural networks

Systems and methods for protecting neural network weights

Pipelined pointwise convolution using per-channel convolution operations

Systems and methods for handling padding regions in convolution operations

Point to point connected processing elements with data joiner components

Hardware for floating-point arithmetic in multiple formats

Grouped convolution using point-to-point connected channel convolution engines

High bandwidth memory system with distributed request broadcasting masters

Optimizing NOC performance using crossbars

Three-dimensional convolution pipeline with memory organizer unit

Bypassing zero-value multiplications in a hardware multiplier

Support for different matrix multiplications by selecting adder tree intermediate results

High throughput matrix processor with support for concurrently processing multiple matrices

Systems and methods for reducing data movement during convolution operations in artificial neural networks

High bandwidth memory system with dynamically programmable distribution scheme

High bandwidth memory system with crossbar switch for dynamically programmable distribution scheme

FACEBOOK INC

Circuit and method for computing depthwise convolution

Systems and methods for optimizing power usage for systems within quality-of-service constraints

Systems and methods for efficiently updating neural networks

Dynamic power management for artificial intelligence hardware accelerators

Systems and methods for efficient scaling of quantized integers

Lowering hardware for neural networks

Systems and methods for encoding videos using reference objects

Sparsity-aware hardware accelerators

Mixed-precision processing elements, systems, and methods for computational models

Hardware accelerator pre-configured with coefficients for matrix-transform operations

High bandwidth memory system with distributed request broadcasting masters

Systems and methods for efficiently updating neural networks

Systems and methods for protecting neural network weights

Systems and methods for employing predication in computational models

Systems and methods for employing predication in computational models

Systems and methods for efficient scaling of quantized integers

CHA HUNGSE

Power estimation based on block activity

DIRIL ABDULKADIR UTKU

Efficient tile-based rasterization

ZHONG LEFAN

Thin-line detection apparatus and method

VIVANTE CORP

Efficient tile-based rasterization