Inventor

NAIR KRISHNAKUMAR NARAYANAN

US22 patents

⚠️ This page may combine multiple inventors who share the name “NAIR KRISHNAKUMAR NARAYANAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAIR KRISHNAKUMAR NARAYANAN

META PLATFORMS INC

Systems and methods for reducing power consumption of convolution operations of artificial neural networks

Using a low-bit-width dot product engine to sum high-bit-width numbers

Mapping convolution to a channel convolution engine

Mapping convolution to a partition channel convolution engine

Pipelined pointwise convolution using per-channel convolution operations

Systems and methods for handling padding regions in convolution operations

Systems and methods for reducing power consumption of convolution operations for artificial neural networks

Hardware for floating-point arithmetic in multiple formats

Grouped convolution using point-to-point connected channel convolution engines

Device and method for flexibly summing matrix values

High bandwidth memory system with distributed request broadcasting masters

Device and method for flexibly summing matrix values

Support for different matrix multiplications by selecting adder tree intermediate results

High throughput matrix processor with support for concurrently processing multiple matrices

Systems and methods for reducing data movement during convolution operations in artificial neural networks

High bandwidth memory system with dynamically programmable distribution scheme

High bandwidth memory system with crossbar switch for dynamically programmable distribution scheme

Matrix processing instruction with optional up/down sampling of matrix

FACEBOOK INC

Memory organization for matrix processing

Systems and methods for reducing power consumption of convolution operations for artificial neural networks

High bandwidth memory system with distributed request broadcasting masters

Floating point multiply hardware using decomposed component numbers