Inventor

CHEN CHII-PING

TW45 patents

⚠️ This page may combine multiple inventors who share the name “CHEN CHII-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN CHII-PING

TAIWAN SEMICONDUCTOR MFG CO LTD

Method for forming semiconductor device with resistive element

Structure and formation method of semiconductor device with resistive element

Semiconductor device structure with resistive element

Structure and formation method of semiconductor device with resistive elements

Semiconductor device structure with resistive element

Barrier free interface between beol interconnects

Inter-wire cavity for low capacitance

Thermal dissipation in semiconductor devices

Semiconductor device structure with resistive element

Thermal dissipation in semiconductor devices

Diffusion barrier layer for conductive via to decrease contact resistance

Self-aligned scheme for semiconductor device and method of forming the same

Inter-wire cavity for low capacitance

Semiconductor devices and method for forming the same

Thermal dissipation in semiconductor devices

Barrier free interface between BEOL interconnects

Method for forming a semiconductor structure by diffusing manganese from a seed layer to a barrier layer

Semiconductor devices and method for forming the same

Semiconductor device structure with resistive element

Method for manufacturing semiconductor structure with resistive elements

Semiconductor device structure with resistive element

Semiconductor device structure with resistive elements

Self-aligned scheme for semiconductor device and method of forming the same

Self-aligned scheme for semiconductor device and method of forming the same

Diffusion barrier layer for conductive via to decrease contact resistance

Self-aligned scheme for semiconductor device and method of forming the same

Self-aligned scheme for semiconductor device and method of forming the same

Diffusion barrier layer for conductive via to decrease contact resistance

Semiconductor device and layout method

Forming interconnect structures in semiconductor devices

TAIWAN SEMICONDUCTOR MFG

Feed forward process control method for adjusting metal line Rs

System and method for multi-stage process control in film removal

Methods of forming integrated circuits

Methods of making integrated circuits including air gaps around interconnect structures

Mask assignment optimization

Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof

CHEN CHII-PING

Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof

Integrated circuit including a gate and a metallic connecting line

CHIH MING-HUI

Method and apparatus of patterning semiconductor device

Method and apparatus of patterning semiconductor device

HUANG CHENG-LIN

Partial air gap formation for providing interconnect isolation in integrated circuits

TSAI HSIN-YI

Method and apparatus of forming a via

LIANG MING-CHUNG

Integrated circuits and methods for forming the integrated circuits

YANG JIING-FENG

Mask treatment for double patterning design

LU LEE-CHUNG

Interconnect structure having smaller transition layer via