Inventor

HAUKNESS BRENT

US54 patents

⚠️ This page may combine multiple inventors who share the name “HAUKNESS BRENT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAUKNESS BRENT

RAMBUS INC

Memory device and repair method with column-based error code tracking

Unsuccessful write retry buffer

Protocol for refresh between a memory controller and a memory device

Resistance change memory cell circuits and methods

Resistance change memory cell circuits and methods

Resistance change memory cell circuits and methods

Reducing memory refresh exit time

Memory controller and memory device command protocol

Memory disturbance recovery mechanism

Protocol for refresh between a memory controller and a memory device

Unsuccessful write retry buffer

Memory device and repair method with column-based error code tracking

Protocol for refresh between a memory controller and a memory device

Protocol for refresh between a memory controller and a memory

Memory pre-characterization

Memory controller and memory device command protocol

Protocol for refresh between a memory controller and a memory device

Unsuccessful write retry buffer

Deterministic operation of storage class memory

Unsuccessful write retry buffer

Protocol for refresh between a memory controller and a memory device

Deterministic operation of storage class memory

Deterministic operation of storage class memory

Unsuccessful write retry buffer

Memory device and repair method with column-based error code tracking

Deterministic operation of storage class memory

HEFEI RELIANCE MEMORY LTD

Techniques for initializing resistive memory devices by applying voltages with different polarities

RRAM write using a ramp control circuit

Techniques for initializing resistive memory devices by applying different polarity voltages across resistance change material

Adaptive memory cell write conditions

Method of RRAM write ramping voltage in intervals

Techniques for initializing resistive memory devices by applying voltages with different polarities

Adaptive memory cell write conditions

Method of RRAM write ramping voltage in intervals

Adaptive memory cell write conditions

Method of RRAM WRITE ramping voltage in intervals

Resistance change memory cell circuits and methods

SANDISK 3D LLC

Apparatus and methods for adaptive trip point detection

Methods and apparatus for employing redundant arrays to configure non-volatile memory

Methods and apparatus for employing redundant arrays to configure non-volatile memory

Methods for adaptive trip point detection

Apparatus for adaptive trip point detection

Methods and apparatus for using a configuration array similar to an associated data array

Methods and apparatus for using a configuration array similar to an associated data array

HAUKNESS BRENT

Resistance change memory cell circuits and methods

Flash memory timing pre-characterization

KIM JAEHA

Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency

KOYA YOSHIHITO

Multilevel DRAM

THORP TYLER

Electronic library for managing data on removable storage devices

MICRON TECHNOLOGY INC

Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode current mirrors