Inventor

CAYWOOD JOHN

US12 patents

⚠️ This page may combine multiple inventors who share the name “CAYWOOD JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EASTMAN KODAK CO

2 patents

US5270980ADec 14, 1993

Sector erasable flash EEPROM

EASTMAN KODAK CO60 citations96

US5621738AApr 15, 1997

Method for programming flash EEPROM devices

EASTMAN KODAK CO42 citations92

XICOR INC

2 patents

US5153880AOct 6, 1992

Field-programmable redundancy apparatus for memory arrays

XICOR INC152 citations96

US5161157ANov 3, 1992

Field-programmable redundancy apparatus for memory arrays

XICOR INC84 citations95

JOHN MILLARD AND PAMELA ANN CA

2 patents

US6411545B1Jun 25, 2002

Non-volatile latch

JOHN MILLARD AND PAMELA ANN CA59 citations94

US6451652B1Sep 17, 2002

Method for forming an EEPROM cell together with transistor for peripheral circuits

JOHN MILLARD AND PAMELA ANN CA34 citations91

CAYWOOD JOHN M

1 patent

US6534816B1Mar 18, 2003

Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell

CAYWOOD JOHN M68 citations95

CREDENCE SYSTEMS CORP

1 patent

US5974579AOct 26, 1999

Efficient built-in self test for embedded memories with differing address spaces

CREDENCE SYSTEMS CORP74 citations94

CAYWOOD JOHN

1 patent

US5235544AAug 10, 1993

Flash EPROM cell and method for operating same

CAYWOOD JOHN93 citations94

HEURISTICS PHYSICS LAB INC

1 patent

US6745370B1Jun 1, 2004

Method for selecting an optimal level of redundancy in the design of memories

HEURISTICS PHYSICS LAB INC29 citations89

HEURISTIC PHYSICS LAB

1 patent

US6096093AAug 1, 2000

Method for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuits

HEURISTIC PHYSICS LAB24 citations85

HPL TECHNOLOGIES INC

1 patent

US6780656B2Aug 24, 2004

Correction of overlay offset between inspection layers

HPL TECHNOLOGIES INC2 citations58