Inventor
CHAVALI SRI CHAITRA JYOTSNA
US28 patents
Patents
28 patentsUS10424530B1Sep 24, 2019
Electrical interconnections with improved compliance due to stress relaxation and method of making
INTEL CORP28 citations93
US10658765B2May 19, 2020
Edge-firing antenna walls built into substrate
INTEL CORP2 citations73
US9953959B1Apr 24, 2018
Metal protected fan-out cavity
INTEL CORP4 citations73
US10624213B1Apr 14, 2020
Asymmetric electronic substrate and method of manufacture
INTEL CORP5 citations72
US10424561B2Sep 24, 2019
Integrated circuit structures with recessed conductive contacts for package on package
INTEL CORP2 citations72
US9865568B2Jan 9, 2018
Integrated circuit structures with recessed conductive contacts for package on package
INTEL CORP3 citations72
US11107757B2Aug 31, 2021
Integrated circuit structures in package substrates
INTEL CORP2 citations71
US10685850B2Jun 16, 2020
High density organic interconnect structures
INTEL CORP3 citations71
US10672693B2Jun 2, 2020
Integrated circuit structures in package substrates
INTEL CORP2 citations71
US11869842B2Jan 9, 2024
Scalable high speed high bandwidth IO signaling package architecture and method of making
INTEL CORP2 citations70
US12586906B2Mar 24, 2026
Antenna package using ball attach array to connect antenna and base substrates
INTEL CORP0 citations62
US12132015B2Oct 29, 2024
Package embedded magnetic inductor structures and manufacturing techniques for 5-50 MHZ SMPS operations
INTEL CORP1 citations62
US11870163B2Jan 9, 2024
Antenna package using ball attach array to connect antenna and base substrates
INTEL CORP0 citations62
US11664313B2May 30, 2023
Microelectronic device including fiber-containing build-up layers
INTEL CORP0 citations62
US11004792B2May 11, 2021
Microelectronic device including fiber-containing build-up layers
INTEL CORP0 citations62
US10980129B2Apr 13, 2021
Asymmetric electronic substrate and method of manufacture
INTEL CORP0 citations62
US10903137B2Jan 26, 2021
Electrical interconnections with improved compliance due to stress relaxation and method of making
INTEL CORP0 citations62
US12334242B2Jun 17, 2025
Coreless electronic substrates having embedded inductors
INTEL CORP0 citations61
US12062551B2Aug 13, 2024
High density organic interconnect structures
INTEL CORP0 citations61
US11631595B2Apr 18, 2023
High density organic interconnect structures
INTEL CORP0 citations61
US11276634B2Mar 15, 2022
High density package substrate formed with dielectric bi-layer
INTEL CORP0 citations61
US11195727B2Dec 7, 2021
High density organic interconnect structures
INTEL CORP0 citations61
US11804426B2Oct 31, 2023
Integrated circuit structures in package substrates
INTEL CORP0 citations60
US11764150B2Sep 19, 2023
Inductors for package substrates
INTEL CORP0 citations60
US12261124B2Mar 25, 2025
Embedded die architecture and method of making
INTEL CORP0 citations52
US11721632B2Aug 8, 2023
Hybrid core substrate architecture for high speed signaling and FLI/SLI reliability and its making
INTEL CORP0 citations51
US12033930B2Jul 9, 2024
Selectively roughened copper architectures for low insertion loss conductive features
INTEL CORP0 citations47
US12592334B2Mar 31, 2026
Stacked magnetic inductor and method
INTEL CORP0 citations46