Inventor
KARAKULAK SEYHAN
US15 patents
⚠️ This page may combine multiple inventors who share the name “KARAKULAK SEYHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
WESTERN DIGITAL TECH INC
7 patentsUS10566061B2Feb 18, 2020
Calibrating optimal read levels
WESTERN DIGITAL TECH INC12 citations85
US9905302B2Feb 27, 2018
Read level grouping algorithms for increased flash performance
WESTERN DIGITAL TECH INC14 citations83
US10387246B2Aug 20, 2019
Method and system for scanning for erased flash memory pages
WESTERN DIGITAL TECH INC1 citations72
US11488673B2Nov 1, 2022
Calibrating optimal read levels
WESTERN DIGITAL TECH INC0 citations62
US11815996B2Nov 14, 2023
Method and system for identifying erased memory areas
WESTERN DIGITAL TECH INC0 citations61
US11327837B2May 10, 2022
Method and system for identifying erased memory areas
WESTERN DIGITAL TECH INC0 citations61
US10884854B2Jan 5, 2021
Method and system for identifying erased memory areas
WESTERN DIGITAL TECH INC0 citations61
HGST Netherlands BV
3 patentsUS9720754B2Aug 1, 2017
Read level grouping for increased flash performance
HGST Netherlands BV40 citations93
US9576671B2Feb 21, 2017
Calibrating optimal read levels
HGST Netherlands BV29 citations93
US9343170B2May 17, 2016
Word-line inter-cell interference detector in flash system
HGST Netherlands BV0 citations51
SK HYNIX INC
3 patentsUS11574698B1Feb 7, 2023
Compressing deep neural networks used in memory devices
SK HYNIX INC2 citations73
US11881869B1Jan 23, 2024
Asymmetric bit errors in low-density parity-check codes for non-volatile memory devices
SK HYNIX INC0 citations52
US11621727B2Apr 4, 2023
Decoding systems and methods for local reinforcement
SK HYNIX INC0 citations52