Inventor

BLAKE TERENCE G W

US16 patents

⚠️ This page may combine multiple inventors who share the name “BLAKE TERENCE G W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEXAS INSTRUMENTS INC

15 patents

US4965213AOct 23, 1990

Silicon-on-insulator transistor with body node to source node connection

TEXAS INSTRUMENTS INC110 citations96

US4946799AAug 7, 1990

Process for making high performance silicon-on-insulator transistor with body node to source node connection

TEXAS INSTRUMENTS INC141 citations96

US4906587AMar 6, 1990

Making a silicon-on-insulator transistor with selectable body node to source node connection

TEXAS INSTRUMENTS INC115 citations96

US4899202AFeb 6, 1990

High performance silicon-on-insulator transistor with body node to source node connection

TEXAS INSTRUMENTS INC150 citations96

US6487687B1Nov 26, 2002

Silicon-on-insulator transistor with selectable body node to source node connection

TEXAS INSTRUMENTS INC38 citations92

US4914629AApr 3, 1990

Memory cell including single event upset rate reduction circuitry

TEXAS INSTRUMENTS INC23 citations92

US4912675AMar 27, 1990

Single event upset hardened memory cell

TEXAS INSTRUMENTS INC41 citations92

US5079604AJan 7, 1992

SOI layout for low resistance gate

TEXAS INSTRUMENTS INC3 citations63

US8472229B2Jun 25, 2013

Array-based integrated circuit with reduced proximity effects

TEXAS INSTRUMENTS INC1 citations52

DENG XIAOWEI

1 patent

US8472228B2Jun 25, 2013

Array-based integrated circuit with reduced proximity effects

DENG XIAOWEI1 citations52

BLAKE TERENCE G W

TEXAS INSTRUMENTS INC

Silicon-on-insulator transistor with body node to source node connection

Process for making high performance silicon-on-insulator transistor with body node to source node connection

Making a silicon-on-insulator transistor with selectable body node to source node connection

High performance silicon-on-insulator transistor with body node to source node connection

Voltage level shifter with testable cascode devices

Output buffer with switching PMOS drivers

Output buffer having quasi-failsafe operation

Output buffer providing testability

Memory cell with capacitance for single event upset protection

Memory cell with capacitance for single event upset protection

Silicon-on-insulator transistor with selectable body node to source node connection

Memory cell including single event upset rate reduction circuitry

Single event upset hardened memory cell

SOI layout for low resistance gate

Array-based integrated circuit with reduced proximity effects

DENG XIAOWEI

Array-based integrated circuit with reduced proximity effects