Inventor
TRAN DAN T
US7 patents
Patents
7 patentsUS5511224AApr 23, 1996
Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories
UNISYS CORP101 citations94
US5598421AJan 28, 1997
Method and system for tracking the state of each one of multiple JTAG chains used in testing the logic of intergrated circuits
UNISYS CORP60 citations93
US5293621AMar 8, 1994
Varying wait interval retry apparatus and method for preventing bus lockout
UNISYS CORP28 citations92
US5553249ASep 3, 1996
Dual bus adaptable data path interface system
UNISYS CORP21 citations90
US5293496AMar 8, 1994
Inhibit write apparatus and method for preventing bus lockout
UNISYS CORP12 citations73
US5444722AAug 22, 1995
Memory module with address error detection
UNISYS CORP9 citations72
US5495573AFeb 27, 1996
Error logging system with clock rate translation
UNISYS CORP13 citations71