Inventor

MAYER ULRICH

DE62 patents

⚠️ This page may combine multiple inventors who share the name “MAYER ULRICH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAYER ULRICH

IBM

Multiple parallel programmable finite state machines using a shared transition table

Translation support for a virtual cache

Cache structure using a logical directory

Cache structure using a logical directory

Semi-exclusive second-level branch target buffer

Operating different processor cache levels

Techniques for monitoring a shared hardware resource

Computer system software/firmware and a processor unit with a security module

Translation support for a virtual cache

Operating different processor cache levels

Method and arrangement for saving cache power

Method and arrangement for saving cache power

Techniques for monitoring a shared hardware resource

Remote access array

Method and system for changing a description for a state transition function of a state machine engine

Method and apparatus for an efficient TLB lookup

Reduced simulation verification complexity of cache purge

Performing processing using hardware counters in a computer system

Translation support for a virtual cache

Cache structure using a logical directory

Translation support for a virtual cache

Computer system software/firmware and a processor unit with a security module

Computer system software/firmware and a processor unit with a security module

Selectively blocking branch prediction for a predetermined number of instructions

Selectively blocking branch prediction for a predetermined number of instructions

Selectively blocking branch prediction for a predetermined number of instructions

Asynchronous lookahead hierarchical branch prediction

Branch target buffer preload table

Instruction filtering

Method and arrangement for saving cache power

Filtering of redundantly scheduled write passes

Operating different processor cache levels

BOSCH GMBH ROBERT

Resetting circuit for microprocessors

Method of adjusting the composition of the operating mixture for an internal combustion engine

Method of controlling ignition in a multicylinder internal combustion engine

Ignition system for an internal combustion engine

Method and arrangement for diagnosing the open-loop control of the tank-venting valve in combination with the open-loop control of an internal combustion engine

Ignition circuit monitoring in an internal combustion engine

Device for controlling at least one throttle cross-section at a control opening

BONANNO JAMES J

Asynchronous lookahead hierarchical branch prediction

Selectively blocking branch prediction for a predetermined number of instructions

Second-level branch target buffer bulk transfer filtering

Branch target buffer preload table

Semi-exclusive second-level branch target buffer

Instruction filtering

MAYER ULRICH

Apparatus and method for operating a symmetric cipher engine in cipher-block chaining mode

Debugging for multiple errors in a microprocessor environment

KOEHLER THOMAS

Multiprocessor electronic circuit including a plurality of processors and electronic data processing system

GLOBALFOUNDRIES INC

Particle reduction in PECVD processes for depositing low-k material by using a plasma assisted post-deposition step

FRITZ ROLF K

Virtual multiple instance extended finite state machines with wait rooms and/or wait queues