Inventor

HUANG CHENG-LIN

TW108 patents

⚠️ This page may combine multiple inventors who share the name “HUANG CHENG-LIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG CHENG-LIN

TAIWAN SEMICONDUCTOR MFG CO LTD

Metal oxide layered structure and methods of forming the same

Fan-out package and methods of forming thereof

Metal oxide layered structure and methods of forming the same

Methods of forming multiple conductive features in semiconductor devices in a same formation process

Integrated fan-out package on package structure and methods of forming same

Chip package with thermal dissipation structure and method for forming the same

Structure and formation method for chip package

Packaging structures and methods with a metal pillar

Semiconductor structure having an air-gap region and a method of manufacturing the same

Non-vertical through-via in package

Method for forming semiconductor device structure with bumps

Semiconductor die singulation and structures formed thereby

Semiconductor die singulation and structures formed thereby

Metal oxide layered structure and methods of forming the same

Semiconductor die singulation and structures formed thereby

Semiconductor package assembly, semiconductor package and forming method thereof

Methods for forming fan-out package structure

Package structure with through vias

Structure and formation method of chip package with fan-out feature

Chip package structure

Non-vertical through-via in package

TAIWAN SEMICONDUCTOR MFG

Semiconductor structure having an air-gap region and a method of manufacturing the same

Method of barrier-less integration with copper alloy

Barrier-free copper interconnect

Integrated circuit structure having dies with connectors

Cleaning processes in the formation of integrated circuit interconnect structures

Barrier structure for semiconductor devices

Bump structures for semiconductor package

Barrier free copper interconnect by multi-layer copper seed

Reducing resistivity in interconnect structures of integrated circuits

Multi-step Cu seed layer formation for improving sidewall coverage

Barrier layer and fabrication method thereof

Method for high kinetic energy plasma barrier deposition

Reducing resistivity in interconnect structures by forming an inter-layer

High performance metallization cap layer

Barrier-less integration with copper alloy

Barrier metal re-distribution process for resistivity reduction

Method for simultaneous degas and baking in copper damascene process

Method of making a semiconductor device including barrier layers for copper interconnect

Method of forming a protective layer included in metal filled semiconductor features

LIN JING-CHENG

Packages including active dies and dummy dies and methods for forming the same

Copper bump structures having sidewall protection layers

Method of three dimensional integrated circuit assembly

SHUE SHAU-LIN

Methods for via structure with improved reliability

Via structure with improved reliability

YU CHEN-HUA

Connector design for packaging integrated circuits

HUANG CHENG-LIN

Partial air gap formation for providing interconnect isolation in integrated circuits

SU SHU-HUI

Semiconductor structure having an air-gap region and a method of manufacturing the same

BROGENT TECH INC

Rotary dynamic simulation device and audiovisual apparatus using the same

LIU NAI-WEI

Barrier layers for copper interconnect