Inventor

PARK KEE

US28 patents

⚠️ This page may combine multiple inventors who share the name “PARK KEE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARK KEE

INTEGRATED DEVICE TECH

Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same

Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same

Content addressable memory (CAM) devices having adjustable match line precharge circuits therein

Content addressable memory (CAM) devices having speed adjustable match line signal repeaters therein

Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein

DRAM-based CAM cell with shared bitlines

Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors

High speed NAND-type content addressable memory (CAM)

Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same

Content addressable memory (CAM) devices with block select and pipelined virtual sector look-up control and methods of operating same

Content addressable memory (CAM) devices that utilize segmented match lines and word lines to support pipelined search and write operations and methods of operating same

Content addressable memory (CAM) devices that utilize dual-capture match line signal repeaters to achieve desired speed/power tradeoff and methods of operating same

Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio

Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same

Content addressable memory (CAM) devices having CAM array blocks therein that perform pipelined and interleaved search, write and read operations and methods of operating same

Variable width wordline pulses in a memory device

Content addressable and random access memory devices having high-speed sense amplifiers therein with low power consumption requirements

Memory device layout

Multi-bank content addressable memory (CAM) devices having segment-based priority resolution circuits therein and methods operating same

Low power content addressable memory array (CAM) and method of operating same

Multi-bank content addressable memory (CAM) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same

NETLOGIC MICROSYSTEMS INC

Content addressable memory (CAM) array capable of implementing read or write operations during search operations

Encoding data for storage in a content addressable memory

Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same

Separate CAM core power supply for power saving

PARK KEE

Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors

Encoding data for storage in a content addressable memory

INTEGRATED DEVICE TECHNOLOGY L

Content addressable memories (CAM) having low power dynamic match line sensing circuits therein