Inventor

SUN YANNING

US46 patents

⚠️ This page may combine multiple inventors who share the name “SUN YANNING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUN YANNING

IBM

III-V finFETs on silicon substrate

High-K spacer for extension-free CMOS devices with high mobility channel materials

Dual-semiconductor complementary metal-oxide-semiconductor device

III-V device with overlapped extension regions using replacement gate

Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics

Asymmetric III-V MOSFET on silicon substrate

Dual-semiconductor complementary metal-oxide-semiconductor device

Asymmetric III-V MOSFET on silicon substrate

Reduced current leakage semiconductor device

Overlapped III-V finFET with doped semiconductor extensions

III-V device with overlapped extension regions using replacement gate

III-V transistor device with self-aligned doped bottom barrier

III-V MOSFET with self-aligned diffusion barrier

Reduced current leakage semiconductor device

Preparation of low defect density of III-V on Si for device fabrication

III-V semiconductor device having self-aligned contacts

Overlapped III-V finfet with doped semiconductor extensions

III-V FET device with overlapped extension regions using gate last

Guiding structures for fabrication of angled features in a semiconductor device

Preparation of low defect density of III-V on Si for device fabrication

Fabrication of asymmetric mandrel structures in semiconductor device

Low external resistance channels in III-V semiconductor devices

III-V MOSFET with self-aligned diffusion barrier

Self-aligned heterojunction field effect transistor

III-V field effect transistor on a dielectric layer

Preparation of low defect density of III-V on Si for device fabrication

III-V transistor device with self-aligned doped bottom barrier

Planar III-V field effect transistor (FET) on dielectric layer

III-V MOSFET with self-aligned diffusion barrier

Low external resistance channels in III-V semiconductor devices

Semiconductor lateral sidewall growth from a semiconductor pillar

Self-aligned heterojunction field effect transistor

Reduced current leakage semiconductor device

III-V field effect transistor on a dielectric layer

III-V semiconductor device having self-aligned contacts

Planar III-V field effect transistor (FET) on dielectric layer

Planar semiconductor growth on III-V material

III-V FET device with overlapped extension regions using gate last

GLOBALFOUNDRIES INC

Multiple via structure and method

Structure and method for CMP-free III-V isolation

III-V semiconductor device having self-aligned contacts

Planar semiconductor growth on III-V material

BABICH KATHERINA

Method to improve nucleation of materials on graphene and carbon nanotubes

Method to improve nucleation of materials on graphene and carbon nanotubes

GUO DECHAO

Schottky junction si nanowire field-effect bio-sensor/molecule detector

LAVOIE CHRISTIAN

Interface engineering to optimize metal-III-V contacts