Inventor · disambiguated record
William S. Jaffe
Also filed as: JAFFE WILLIAM S
8 granted patents·2 pending applications·392 citations·filing 1990–2021
90Inventor score
Top patents by PatentIndex Score
10 records- 0181US5448715ADual clock domain interface between CPU and memory busHEWLETT PACKARD CO·Filed 1992·Granted Sep 5, 1995·107 cites·21 claims
- 0279US5287477AMemory-resource-driven arbitrationHEWLETT PACKARD CO·Filed 1991·Granted Feb 15, 1994·82 cites·10 claims
- 0378US5097157AFast cmos bus receiver for detecting low voltage swingsHEWLETT PACKARD CO·Filed 1990·Granted Mar 17, 1992·39 cites·22 claims
- 0465US5293607AFlexible N-way memory interleavingHEWLETT PACKARD CO·Filed 1991·Granted Mar 8, 1994·44 cites·9 claims
- 0561US5265223APreservation of priority in computer bus arbitrationHEWLETT PACKARD CO·Filed 1992·Granted Nov 23, 1993·38 cites·9 claims
- 0660US2021167038A1Dual in-line memory moduleHEWLETT PACKARD ENTPR DEV LP·Filed 2021·Application pending·0 cites
- 0758US5257356AMethod of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer systemHEWLETT PACKARD CO·Filed 1991·Granted Oct 26, 1993·34 cites·15 claims
- 0857US5249297AMethods and apparatus for carrying out transactions in a computer systemHEWLETT PACKARD CO·Filed 1991·Granted Sep 28, 1993·32 cites·20 claims
- 0946US2020066676A1Dual in-line memory moduleHEWLETT PACKARD ENTPR DEV LP·Filed 2016·Application pending·0 cites
- 1044US5255373ADecreasing average time to access a computer bus by eliminating arbitration delay when the bus is idleHEWLETT PACKARD CO·Filed 1991·Granted Oct 19, 1993·16 cites·5 claims
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