Inventor

MAY CHARLES E

US113 patents

⚠️ This page may combine multiple inventors who share the name “MAY CHARLES E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAY CHARLES E

ADVANCED MICRO DEVICES INC

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices

Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process

Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions

Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths

Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen

Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography

Transistor having enhanced metal silicide and a self-aligned gate electrode

Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication

Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density

Ultrathin silicon nitride containing sidewall spacers for improved transistor performance

Ion beam milling to generate custom reticles

Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process

Transistor having a metal silicide self-aligned to the gate

Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy

Process for formation of isolation trenches with high-K gate dielectrics

Integration of high K spacers for dual gate oxide channel fabrication technique

Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer

Semiconductor topography having improved active device isolation and reduced dopant migration

Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same

Buried local interconnect

Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance

High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure

Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor

Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length

Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device

Buried trench capacitor

Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate

Semiconductor device with layered doped regions and methods of manufacture

Trench isolation structure partially bound between a pair of low K dielectric structures

Method of making dual channel gate oxide thickness for MOSFET transistor design

Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed

Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface

Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device

Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation

Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench

Method of patterning a metal substrate using spin-on glass as a hard mask

Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure

Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties

Trench isolation structure partially bound between a pair of low K dielectric structures

Rapid thermal anneal system and method including improved temperature sensing and monitoring

Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control

Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios

Method of fabricating ultra thin nitride spacers and device incorporating same

Method for making asymmetrical gate oxide thickness in channel MOSFET region

Semiconductor device with a reduced width gate dielectric and method of making same

LSI LOGIC CORP

Via and metal line interface capable of reducing the incidence of electro-migration induced voids

Process for improving mechanical strength of layers of low k dielectric material

Bond pad design

ADVANCED MICRO SERVICES

Semiconductor device having silicide layers formed using a collimated metal layer