Inventor
ZELICK NANCY M
US12 patents
⚠️ This page may combine multiple inventors who share the name “ZELICK NANCY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS7348284B2Mar 25, 2008
Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
INTEL CORP141 citations99
US7960794B2Jun 14, 2011
Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
INTEL CORP20 citations92
US9391181B2Jul 12, 2016
Lattice mismatched hetero-epitaxial film
INTEL CORP10 citations84
US10249490B2Apr 2, 2019
Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy
INTEL CORP2 citations73
US9640537B2May 2, 2017
Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy
INTEL CORP2 citations73
US11631737B2Apr 18, 2023
Ingaas epi structure and wet etch process for enabling III-v GAA in art trench
INTEL CORP0 citations52
US10756198B2Aug 25, 2020
Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
INTEL CORP0 citations52
US9768269B2Sep 19, 2017
Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
INTEL CORP0 citations52
US9680013B2Jun 13, 2017
Non-planar device having uniaxially strained semiconductor body and method of making same
INTEL CORP0 citations52