Inventor
YAU LEOPOLDO D
US25 patents
⚠️ This page may combine multiple inventors who share the name “YAU LEOPOLDO D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
24 patentsUS6165826ADec 26, 2000
Transistor with low resistance tip and method of fabrication in a CMOS process
INTEL CORP301 citations99
US5783478AJul 21, 1998
Method of frabricating a MOS transistor having a composite gate electrode
INTEL CORP157 citations99
US5625217AApr 29, 1997
MOS transistor having a composite gate electrode and method of fabrication
INTEL CORP162 citations99
US6326664B1Dec 4, 2001
Transistor with ultra shallow tip and method of fabrication
INTEL CORP128 citations98
US5710450AJan 20, 1998
Transistor with ultra shallow tip and method of fabrication
INTEL CORP199 citations98
US5611943AMar 18, 1997
Method and apparatus for conditioning of chemical-mechanical polishing pads
INTEL CORP120 citations98
US4837185AJun 6, 1989
Pulsed dual radio frequency CVD process
INTEL CORP596 citations98
US5554064ASep 10, 1996
Orbital motion chemical-mechanical polishing apparatus and method of fabrication
INTEL CORP149 citations97
US5434093AJul 18, 1995
Inverted spacer transistor
INTEL CORP166 citations97
US5595526AJan 21, 1997
Method and apparatus for endpoint detection in a chemical/mechanical process for polishing a substrate
INTEL CORP91 citations96
US5104819AApr 14, 1992
Fabrication of interpoly dielctric for EPROM-related technologies
INTEL CORP173 citations96
US5863832AJan 26, 1999
Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
INTEL CORP70 citations93
US5244843ASep 14, 1993
Process for forming a thin oxide layer
INTEL CORP57 citations93
US4587138AMay 6, 1986
MOS rear end processing
INTEL CORP75 citations93
US6139404AOct 31, 2000
Apparatus and a method for conditioning a semiconductor wafer polishing pad
INTEL CORP19 citations92
US5488003AJan 30, 1996
Method of making emitter trench BiCMOS using integrated dual layer emitter mask
INTEL CORP26 citations92
US4690728ASep 1, 1987
Pattern delineation of vertical load resistor
INTEL CORP53 citations92
US6095904AAug 1, 2000
Orbital motion chemical-mechanical polishing method and apparatus
INTEL CORP17 citations91
US4786612ANov 22, 1988
Plasma enhanced chemical vapor deposited vertical silicon nitride resistor
INTEL CORP31 citations90
US4755480AJul 5, 1988
Method of making a silicon nitride resistor using plasma enhanced chemical vapor deposition
INTEL CORP46 citations90
US4620986ANov 4, 1986
MOS rear end processing
INTEL CORP33 citations89
US4917044AApr 17, 1990
Electrical contact apparatus for use with plasma or glow discharge reaction chamber
INTEL CORP18 citations73
USRE38674EDec 21, 2004
Process for forming a thin oxide layer
INTEL CORP8 citations71
US5856697AJan 5, 1999
Integrated dual layer emitter mask and emitter trench for BiCMOS processes
INTEL CORP4 citations63