Inventor

BYERS LARRY L

US58 patents

⚠️ This page may combine multiple inventors who share the name “BYERS LARRY L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BYERS LARRY L

UNISYS CORP

Fault tolerant extended processing complex for redundant nonvolatile file caching

System for processing shift, mask, and merge operations in one instruction

Data block check sequence generation and validation in a file cache system

Method and apparatus for storing computer data after a power failure

Microsequencer bus controller system

Initial program load control

Memory access system for pipelined data paths to and from storage

Scientific processor to support a host processor referencing common memory

Method and apparatus for locally generating addressing information for a memory access

Multiple power domain power loss detection and interface disable

Method and apparatus for determining the source and nature of an error within a computer system

Fault tolerant clock distribution system

Method and apparatus for asynchronous device communication

Method and apparatus for isolating an error within a computer system that transfers data via an interface device

Method and apparatus for indicating the severity of a fault within a computer system

System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables

VLSI embedded RAM test

System and method for managing input/output requests using a fairness throttle

Method and apparatus for dynamically testing a memory within a computer system

Multiple interval single phase clock

Fault capture/fault injection system

System and method for detecting faults in storage device addressing logic

Method and apparatus for providing fault detection to a bus within a computer system

Built-in-self-test scheme for testing multiple memory elements

Unconditional clock and automatic refresh logic

Method and apparatus for synchronizing independently executing test lists for design verification

Dedicated point to point fiber optic interface

Four port RAM cell

Bus data transmission verification system

System and method for processing external conditional branch instructions

Stuck fault detection for branch instruction condition signals

System for interconnecting MSUs to a computer system

Activity verification system for memory or logic

Bifurcated register priority system

Logical PCI bus

Multiple width data bus for a microsequencer bus controller system

Transparent flip-flop

Redundant maintenance architecture

Macro level control of an activity switch in a scientific vector processor which processor requires an external executive control program

Processor communications bus having address lines selecting different storage locations based on selected control lines

Architecture for smart control of bi-directional transfer of data

MARVELL INT LTD

Method and system for using an external bus controller in embedded disk controllers

Method and system for embedded disk controllers

Interrupt controller for processing fast and regular interrupts

Servo controller interface module for embedded disk controllers

Method and system for using an external bus controller in embedded disk controllers

SPERRY CORP

High-speed instruction control for vector processors with remapping

Control unit busy queuing

PURDHAM DAVID M

Memory fault injection

QLOGIC CORP

Method and system for monitoring embedded disk controller components