Inventor

OHSHIMA SHIGEO

JP65 patents

⚠️ This page may combine multiple inventors who share the name “OHSHIMA SHIGEO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OHSHIMA SHIGEO

TOSHIBA KK

Semiconductor memory device having a plurality of banks

Semiconductor memory device having a power-down mode

Synchronous semiconductor memory

Synchronous type semiconductor integrated circuit having a delay monitor controlled by a delay control signal obtained in a delay measuring mode

Non-volatile memory device and method for writing data thereto

Fast cycle RAM and data readout method therefor

Semiconductor memory system

Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell

Synchronous semiconductor memory device having dynamic memory cells and operating method thereof

Clock control circuit

Semiconductor memory device which operates in synchronism with a clock signal

Clock control circuit with an input stop circuit

Semiconductor memory device

Semiconductor memory device

Multiport memory with test signal generating circuit controlling data transfer from ram port to sam port

Semiconductor memory device

Semiconductor memory device

MOS TEG structure

Semiconductor integrated circuit

Semiconductor memory device

Method of programming a non-volatile memory device

Semiconductor device and semiconductor memory tester

Semiconductor device, relay chip, and method for producing relay chip

Semiconductor integrated circuit and memory system

Synchronous type semiconductor memory device

Synchronous semiconductor memory device

Clock synchronous circuit

Synchronous semiconductor memory device

Semiconductor memory device

Fast cycle ram having improved data write operation

Fast cycle RAM and data readout method therefor

Semiconductor memory device capable of masking data to be written

Semiconductor memory device

Function selector circuit

Multiport memory with improved timing of word line selection

Serial data transfer circuit for a semiconductor memory device

Operation mode setting circuit for dram

Semiconductor device having reduced potential fluctuations

Integrated circuit with switching noise reduction by feedback

Internal interleaving type semiconductor memory device

Synchronous semiconductor memory device with a plurality of memory banks and method of controlling the same

Synchronous semiconductor memory device

Semiconductor memory device with testable spare columns and rows

Semiconductor memory capable of improving data rewrite speed

Semiconductor memory device having synchronous write driver circuit

Semiconductor memory circuit equipped with a column addressing circuit having a shift register

Semiconductor device having protection circuit

Non-volatile memory device and method for writing data thereto

Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system

SHIMIZU YUUI

Semiconductor device and semiconductor memory tester