Inventor

TAKAYANAGI TOSHINARI

JP37 patents

⚠️ This page may combine multiple inventors who share the name “TAKAYANAGI TOSHINARI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAKAYANAGI TOSHINARI

APPLE INC

Hardware automatic performance state transitions in system on processor sleep and wake events

Power switch ramp rate control using daisy-chained flops

Power switch acceleration scheme for fast wakeup

Hardware automatic performance state transitions in system on processor sleep and wake events

CMOS circuitry with mixed transistor parameters

Systems and methods for determining temperatures of integrated circuits

Control scheme to temporarily raise supply voltage in response to sudden change in current demand

Power switch acceleration scheme for fast wakeup

Dynamic power noise event counter

Control scheme to temporarily raise supply voltage in response to sudden change in current demand

Control scheme to temporarily raise supple voltage in response to sudden change in current demand

Pre-program of clock generation circuit for faster lock coming out of reset

Power droop measurements using analog-to-digital converter during testing

Integrated characterization circuit

TOSHIBA KK

Set-associative cache memory with shared sense amplifiers

Semiconductor memory device

Microprocessor cache redundancy scheme using store buffer

Associative memory system with hit entry detection circuit

Data transfer circuit

Static random access memory including potential control means for writing data in memory cell and write method for memory cell

Adder logic circuit and processor

Logical circuit for detecting a potential

Differential amplifier

Semiconductor memory device having a sensitivity controllable sense amplifier circuit

TAKAYANAGI TOSHINARI

Multi-path power switch scheme for functional block wakeup

Adaptive voltage adjustment based on temperature value

Power switch acceleration scheme for fast wakeup

Temperature compensation in integrated circuit

Threshold-based temperature-dependent power/thermal management with temperature sensor calibration

Power switch ramp rate control using programmable connection to switches

Impedance-based power supply switch optimization

SUN MICROSYSTEMS INC

Negative bias temperature instability (NBTI) preconditioning of matched devices

Multi-ported memory cell

Programmable delay for self-timed-margin

Method and system for timing modeling for custom circuit blocks

Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices

DE CESARE JOSH P

Hardware controlled PLL switching