Inventor

MCCLURE DAVID C

US188 patents

⚠️ This page may combine multiple inventors who share the name “MCCLURE DAVID C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCCLURE DAVID C

SGS THOMSON MICROELECTRONICS

Fault detection for entire wafer stress test

Fuse circuitry to control the propagation delay of an IC

Column redundancy architecture for a read/write memory

Integrated circuit that supports and method for wafer-level testing

Write pass through circuit

Integrated circuit memory with double bitline low special test mode control from output enable

Variable input threshold adjustment

Method and apparatus for programming signal timing

Semiconductor memory with power-on reset controlled latched row line repeaters

Multiple clocked dynamic sense amplifier

Redundancy decoder

Semiconductor memory with improved redundant sense amplifier control

Dual dynamic sense amplifiers for a memory array

Precharging output driver circuit

Compensating delay element for clock generation in a memory device

Redundancy element check in IC memory without programming substitution of redundant elements

Address buffer

Semiconductor memory having improved latched repeaters for memory row line selection

Semiconductor memory with sequenced latched row line repeaters

Semiconductor memory with power-on reset controlled latched row line repeaters

Power-on reset circuit for controlling test mode entry

Integrated circuit having multiple data outputs sharing a resistor network

Semiconductor memory with sequential clocked access codes for test mode entry

Circuit for providing a compensated bias voltage

Circuit for providing a compensated bias voltage

Semiconductor memory with inhibited test mode entry during power-up

Semiconductor memory with multiplexed redundancy

Semiconductor memory with improved test mode

Circuit and method for tracking the start of a write to a memory cell

Constant current source with reduced sensitivity to supply voltage and process variation

Redundancy control

Circuit and method for biasing bit lines

Integrated memory circuit with sequenced bitlines for stress test

Write driver having a test function

Input delay control

Method and apparatus for test mode entry during power up

Circuit for providing a bias voltage compensated for p-channel transistor variations

Low-power read circuit and method for controlling a sense amplifier

ST MICROELECTRONICS INC

Integrated volatile and non-volatile memory

Circuit and method for setting the time duration of a write to a memory cell

Memory having and method for testing redundant memory cells

Integrated volatile and non-volatile memory

Circuit and method for testing a ferroelectric memory device

Self-timed write reset pulse generation

Circuit and method for selecting a signal

Integrated circuit with power dissipation control

Device and method for driving a conductive path with a signal

Integrated-circuit die suitable for wafer-level testing and method for forming the same

Memory-row selector having a test function

Circuit and method for terminating a write to a memory cell