Inventor

GARIBAY JR RAUL A

US36 patents

⚠️ This page may combine multiple inventors who share the name “GARIBAY JR RAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GARIBAY JR RAUL A

NAT SEMICONDUCTOR CORP

System and method of retiring store data from a write buffer

Method of invoking a low power mode in a computer system using a halt instruction

Computer system with low power mode invoked by halt instruction

Address translation unit employing programmable page size

Coherency for write-back cache in a system designed for write-through cache including export-on-hold

Method of identifying and self-modifying code

Instruction-initiated power management method for a pipelined data processor

Signal-initiated method for suspending operation of a pipelined data processor

Pipelined data processor with signal-initiated power management control

Method for controlling power of a microprocessor by asserting and de-asserting a control signal in response conditions associated with the microprocessor entering and exiting low power state respectively

Signal-initiated power management method for a pipelined data processor

System for controlling power of a microprocessor by asserting and de-asserting a control signal in response to condition associated with the microprocessor entering and exiting low power state respectively

Power management method for a pipelined computer system

Pipelined data processor with instruction-initiated power management control

Pipelined computer system with power management control

Instruction-initiated method for suspending operation of a pipelined data processor

CYRIX CORP

Data dependency detection and handling in a microprocessor with write buffer

Microprocessor having power management circuitry with coprocessor support

Microprocessor with externally controllable power management

System and method of retiring store data from a write buffer

Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception

Coherency for write-back cache in a system designed for write-through cache including write-back latency control

In a pipelined processor, setting a segment access indicator during execution stage using exception handling

Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch

Circuit and method for addressing segment descriptor tables

Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol

Address translation unit employing a victim TLB

Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin

Processor with single clock decode architecture employing single microROM

Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window

VIA CYRIX INC

Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline

System and method of retiring misaligned write operands from a write buffer

MYTHIC INC

Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture

Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture

ARTERIS INC

Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks

TEXAS INSTRUMENTS INC

Configurable cache system depending on instruction type