Inventor

CHEN TEH-YI J

US7 patents

⚠️ This page may combine multiple inventors who share the name “CHEN TEH-YI J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PHILIPS CORP

3 patents

US5424567AJun 13, 1995

Protected programmable transistor with reduced parasitic capacitances and method of fabrication

PHILIPS CORP108 citations96

US5486480AJan 23, 1996

Method of fabrication of protected programmable transistor with reduced parasitic capacitances

PHILIPS CORP25 citations91

US5110757AMay 5, 1992

Formation of composite monosilicon/polysilicon layer using reduced-temperature two-step silicon deposition

PHILIPS CORP60 citations88

SIGNETICS CORP

2 patents

US4584205AApr 22, 1986

Method for growing an oxide layer on a silicon surface

SIGNETICS CORP13 citations68

US4653173AMar 31, 1987

Method of manufacturing an insulated gate field effect device

SIGNETICS CORP4 citations61

NORTH AMERICAN PHILIPS CORP SI

1 patent

US4786609ANov 22, 1988

Method of fabricating field-effect transistor utilizing improved gate sidewall spacers

NORTH AMERICAN PHILIPS CORP SI55 citations91

CHEN TEH YI J

1 patent

US5008212AApr 16, 1991

Selective asperity definition technique suitable for use in fabricating floating-gate transistor

CHEN TEH YI J17 citations68