Inventor
BALASINSKI ARTUR
US3 patents
Patents
3 patentsUS6562638B1May 13, 2003
Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
CYPRESS SEMICONDUCTOR CORP69 citations92
US6681376B1Jan 20, 2004
Integrated scheme for semiconductor device verification
CYPRESS SEMICONDUCTOR CORP16 citations82
US7197737B1Mar 27, 2007
Techniques for placing dummy features in an integrated circuit based on dielectric pattern density
CYPRESS SEMICONDUCTOR CORP18 citations77