Inventor

PAREKHJI RUBIN A

IN16 patents

⚠️ This page may combine multiple inventors who share the name “PAREKHJI RUBIN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEXAS INSTRUMENTS INC

13 patents

US7134061B2Nov 7, 2006

At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform

TEXAS INSTRUMENTS INC69 citations95

US9091729B2Jul 28, 2015

Scan chain masking qualification circuit shift register and bit-field decoders

TEXAS INSTRUMENTS INC13 citations92

US8671329B2Mar 11, 2014

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

TEXAS INSTRUMENTS INC17 citations92

US11119152B2Sep 14, 2021

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

TEXAS INSTRUMENTS INC3 citations83

US10591540B2Mar 17, 2020

Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components

TEXAS INSTRUMENTS INC19 citations79

US11592483B2Feb 28, 2023

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

TEXAS INSTRUMENTS INC1 citations72

US6697982B2Feb 24, 2004

Generating netlist test vectors by stripping references to a pseudo input

TEXAS INSTRUMENTS INC8 citations70

US9581645B2Feb 28, 2017

Test circuit providing different levels of concurrency among radio cores

TEXAS INSTRUMENTS INC2 citations66

US11921159B2Mar 5, 2024

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

TEXAS INSTRUMENTS INC0 citations62

US7203880B2Apr 10, 2007

Generating an abbreviated netlist including pseudopin inputs and output nodes

TEXAS INSTRUMENTS INC0 citations48

KUMAR SANJAY

1 patent

US8438344B2May 7, 2013

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

KUMAR SANJAY19 citations91

NARAYANAN PRAKASH

1 patent

US8887018B2Nov 11, 2014

Masking circuit removing unknown bit from cell in scan chain

NARAYANAN PRAKASH19 citations90

SONTAKKE ADESH SHARADRAO

1 patent

US8694276B2Apr 8, 2014

Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure

SONTAKKE ADESH SHARADRAO15 citations83

PAREKHJI RUBIN A

TEXAS INSTRUMENTS INC

At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform

Scan chain masking qualification circuit shift register and bit-field decoders

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

Compressed scan chains with three input mask gates and registers

Compressed scan chains with three input mask gates and registers

Decompressed scan chain masking circuit shift register with log2(n/n) cells

Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Generating netlist test vectors by stripping references to a pseudo input

Test circuit providing different levels of concurrency among radio cores

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Generating an abbreviated netlist including pseudopin inputs and output nodes

KUMAR SANJAY

Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes

NARAYANAN PRAKASH

Masking circuit removing unknown bit from cell in scan chain

SONTAKKE ADESH SHARADRAO

Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure