Inventor

GILMER MARK C

US82 patents

⚠️ This page may combine multiple inventors who share the name “GILMER MARK C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GILMER MARK C

ADVANCED MICRO DEVICES INC

Nitrogenated gate structure for improved transistor performance and method for making same

Semiconductor devices comprised of one or more epitaxial layers

Flash memory device having high permittivity stacked dielectric and fabrication thereof

Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation

Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation

Method of integration of nitrogen bearing high K film

Manufacturing process for reducing feature dimensions in a semiconductor

Transistor having a barrier layer below a high permittivity gate dielectric

Semiconductor device having dual gate electrode material and process of fabrication thereof

Semiconductor trench isolation structure formed substantially within a single chamber

Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate

Enhanced oxynitride gate dielectrics using NF3 gas

Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant

Semiconductor device having reduced polysilicon gate electrode width and method of manufacture thereof

Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices

Advanced isolation structure for high density semiconductor devices

Method of making high performance MOSFET with polished gate and source/drain feature

Integrated circuit having transistors that include insulative punchthrough regions and method of formation

High performance MOSFET and method of forming the same using silicidation and junction implantation prior to gate formation

Method of making a semiconductor device with a multi-level gate structure

CMP of a circlet wafer using disc-like brake polish pads

Semiconductor device having a nitrogen bearing isolation region

Oxide formation technique using thin film silicon deposition

Semiconductor device with a multi-level gate structure and a gate dielectric composed of barium zirconium titanate material

Compound material T gate structure for devices with gate dielectrics having a high dielectric constant

Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length

Diamond etch stop rendered conductive by a gas cluster ion beam implant of titanium

Implanted isolation structure formation for high density CMOS integrated circuits

Method of making a semiconductor device having high performance gate electrode structure

Method of forming ultra-thin oxides with low temperature oxidation

Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate

Gate oxidation technique for deep sub quarter micron transistors

Oxynitride GTE dielectrics using NH3 gas

Method for making nitrogenated gate structure for improved transistor performance

Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces

Method of making ultra thin gate oxide using aluminum oxide

Semiconductor device having a tri-layer gate insulating dielectric

Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode

Method for in-situ cleaning of polysilicon-coated quartz furnaces

Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof

Method of making enhanced trench oxide with low temperature nitrogen integration

Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant

Photoresist application for a circlet wafer

Semiconductor device having an outgassed oxide layer and fabrication thereof

Process of fabricating a semiconductor device having cobalt niobate gate electrode structure

High density mosfet fabrication method with integrated device scaling

Method of forming ultra-thin oxides with low temperature oxidation

Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-K gate electrode design

Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same

ADVANCED MICRON DEVICES INC

Apparatus for performing jet vapor reduction of the thickness of process layers