Inventor
ZAIDI NAZAR A
US19 patents
Patents
19 patentsUS5961630AOct 5, 1999
Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency
INTEL CORP70 citations96
US5996064ANov 30, 1999
Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency
INTEL CORP44 citations92
US7392369B2Jun 24, 2008
Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check
INTEL CORP14 citations91
US5918031AJun 29, 1999
Computer utilizing special micro-operations for encoding of multiple variant code flows
INTEL CORP34 citations86
US5944818AAug 31, 1999
Method and apparatus for accelerated instruction restart in a microprocessor
INTEL CORP17 citations76
US6292882B1Sep 18, 2001
Method and apparatus for filtering valid information for downstream processing
INTEL CORP13 citations73
US6055652AApr 25, 2000
Multiple segment register use with different operand size
INTEL CORP11 citations73
US6049897AApr 11, 2000
Multiple segment register use with different operand size
INTEL CORP7 citations73
US5954814ASep 21, 1999
System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline
INTEL CORP7 citations73
US7062636B2Jun 13, 2006
Ordering scheme with architectural operation decomposed into result producing speculative micro-operation and exception producing architectural micro-operation
INTEL CORP9 citations72
US6405307B1Jun 11, 2002
Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipeline
INTEL CORP9 citations72
US5961615AOct 5, 1999
Method and apparatus for queuing data
INTEL CORP8 citations72
US6044456AMar 28, 2000
Electronic system and method for maintaining synchronization of multiple front-end pipelines
INTEL CORP11 citations69
US6363408B1Mar 26, 2002
Method and apparatus for summing selected bits from a plurality of machine vectors
INTEL CORP2 citations62
US6237088B1May 22, 2001
System and method for tracking in-flight instructions in a pipeline
INTEL CORP3 citations62
US7330963B2Feb 12, 2008
Resolving all previous potentially excepting architectural operations before issuing store architectural operation
INTEL CORP4 citations61
US6574689B1Jun 3, 2003
Method and apparatus for live-lock prevention
INTEL CORP5 citations61
US6216221B1Apr 10, 2001
Method and apparatus for expanding instructions
INTEL CORP4 citations61
US6523106B1Feb 18, 2003
Method and apparatus for efficient pipelining
INTEL CORP5 citations57