Inventor
CHOW TAT-SING P
US11 patents
Patents
11 patentsUS4823176AApr 18, 1989
Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
GEN ELECTRIC165 citations99
US4801986AJan 31, 1989
Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
GEN ELECTRIC329 citations99
US5510281AApr 23, 1996
Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
GEN ELECTRIC160 citations98
US4901127AFeb 13, 1990
Circuit including a combined insulated gate bipolar transistor/MOSFET
GEN ELECTRIC59 citations96
US4620211AOct 28, 1986
Method of reducing the current gain of an inherent bipolar transistor in an insulated-gate semiconductor device and resulting devices
GEN ELECTRIC71 citations96
US4998151AMar 5, 1991
Power field effect devices having small cell size and low contact resistance
GEN ELECTRIC71 citations95
US4862242AAug 29, 1989
Semiconductor wafer with an electrically-isolated semiconductor device
GEN ELECTRIC25 citations92
US4333965AJun 8, 1982
Method of making integrated circuits
GEN ELECTRIC21 citations82
US4227944AOct 14, 1980
Methods of making composite conductive structures in integrated circuits
GEN ELECTRIC21 citations81
US4717679AJan 5, 1988
Minimal mask process for fabricating a lateral insulated gate semiconductor device
GEN ELECTRIC10 citations73
US4429011AJan 31, 1984
Composite conductive structures and method of making same
GEN ELECTRIC12 citations73