Inventor

IACOPONI JOHN A

US42 patents

⚠️ This page may combine multiple inventors who share the name “IACOPONI JOHN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IACOPONI JOHN A

ADVANCED MICRO DEVICES INC

Method for forming semiconductor seed layers by inert gas sputter etching

Electroplating uniformity by diffuser design

Deposition of a conductor in a via hole or trench

Dual barrier and conductor deposition in a dual damascene process for semiconductors

Nitrogen treatment for metal-silicide contact

Backside contact for integrated circuit and method of forming same

Method and apparatus for forming an under bump metallurgy layer

Alloy barrier layers for semiconductors

Method for ramped current density plating of semiconductor vias and trenches

Semiconductor interconnect interface processing by high temperature deposition

Creation of an etch hardmask by spin-on technique

Method for implanting semiconductor conductive layers

Low dielectric constant coating of conductive material in a damascene process for semiconductors

Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient

Method of forming semiconductor devices by microwave curing of low-k dielectric films

Method for forming openings for conductive interconnects

Method for forming copper interconnects

Method for forming semiconductor seed layers by high bias deposition

Multi-stage method for forming optimized semiconductor seed layers

Borderless vias with CVD barrier layer

Dual barrier and conductor deposition in a dual damascene process for semiconductors

Semiconductor interconnect interface processing by high pressure deposition

Borderless vias with CVD barrier layer

Method and apparatus for detecting the endpoint of a chemical-mechanical polishing operation using optical techniques

Contact each methodology and integration scheme

Integration of low-K SiOF as inter-layer dielectric for AL-gapfill application

Method for forming in-situ implanted semiconductor barrier layers

Method and apparatus for detecting voltage contrast in a semiconductor wafer

Variable grain size in conductors for semiconductor vias and trenches

Barrier materials for metal interconnect in a semiconductor device

Semiconductor metalization barrier and manufacturing method therefor

Strength coil for ionized copper plasma deposition

Barrier materials for metal interconnect

Metal-semiconductor contact formed using nitrogen plasma

Test structure for providing depth of polish feedback

Manufacturing method for semiconductor metalization barrier

Method and apparatus for enhancing endpoint detection of a via etch

GLOBALFOUNDRIES INC

Methods of forming semiconductor device with self-aligned contact elements and the resulting devices

Semiconductor device configured for avoiding electrical shorting

GLOBALFOUNDARIES INC

Methods of forming semiconductor device with self-aligned contact elements and the resulting devices

STRECK CHRISTOF

Enhancing structural integrity and defining critical dimensions of metallization systems of semiconductor devices by using ALD techniques

RYAN E TODD

Method for depositing a conductive capping layer on metal lines